M53017EVB.h 6.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuation settings for the Freescale MCF53017EVB.
  4. *
  5. * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
  6. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  7. */
  8. /*
  9. * board/config.h - configuration options, board specific
  10. */
  11. #ifndef _M53017EVB_H
  12. #define _M53017EVB_H
  13. /*
  14. * High Level Configuration Options
  15. * (easy to change)
  16. */
  17. #define CONFIG_MCFUART
  18. #define CONFIG_SYS_UART_PORT (0)
  19. #undef CONFIG_WATCHDOG
  20. #define CONFIG_WATCHDOG_TIMEOUT 5000
  21. #define CONFIG_SYS_UNIFY_CACHE
  22. #define CONFIG_MCFFEC
  23. #ifdef CONFIG_MCFFEC
  24. # define CONFIG_MII 1
  25. # define CONFIG_MII_INIT 1
  26. # define CONFIG_SYS_DISCOVER_PHY
  27. # define CONFIG_SYS_RX_ETH_BUFFER 8
  28. # define CONFIG_SYS_TX_ETH_BUFFER 8
  29. # define CONFIG_SYS_FEC_BUF_USE_SRAM
  30. # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  31. # define CONFIG_HAS_ETH1
  32. # define CONFIG_SYS_FEC0_PINMUX 0
  33. # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
  34. # define CONFIG_SYS_FEC1_PINMUX 0
  35. # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE
  36. # define MCFFEC_TOUT_LOOP 50000
  37. /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  38. # ifndef CONFIG_SYS_DISCOVER_PHY
  39. # define FECDUPLEX FULL
  40. # define FECSPEED _100BASET
  41. # else
  42. # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  43. # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  44. # endif
  45. # endif /* CONFIG_SYS_DISCOVER_PHY */
  46. #endif
  47. #define CONFIG_MCFRTC
  48. #undef RTC_DEBUG
  49. #define CONFIG_SYS_RTC_CNT (0x8000)
  50. #define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
  51. /* Timer */
  52. #define CONFIG_MCFTMR
  53. #undef CONFIG_MCFPIT
  54. /* I2C */
  55. #define CONFIG_SYS_I2C
  56. #define CONFIG_SYS_I2C_FSL
  57. #define CONFIG_SYS_FSL_I2C_SPEED 80000
  58. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  59. #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
  60. #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
  61. #define CONFIG_UDP_CHECKSUM
  62. #ifdef CONFIG_MCFFEC
  63. # define CONFIG_IPADDR 192.162.1.2
  64. # define CONFIG_NETMASK 255.255.255.0
  65. # define CONFIG_SERVERIP 192.162.1.1
  66. # define CONFIG_GATEWAYIP 192.162.1.1
  67. #endif /* FEC_ENET */
  68. #define CONFIG_HOSTNAME "M53017"
  69. #define CONFIG_EXTRA_ENV_SETTINGS \
  70. "netdev=eth0\0" \
  71. "loadaddr=40010000\0" \
  72. "u-boot=u-boot.bin\0" \
  73. "load=tftp ${loadaddr) ${u-boot}\0" \
  74. "upd=run load; run prog\0" \
  75. "prog=prot off 0 3ffff;" \
  76. "era 0 3ffff;" \
  77. "cp.b ${loadaddr} 0 ${filesize};" \
  78. "save\0" \
  79. ""
  80. #define CONFIG_PRAM 512 /* 512 KB */
  81. #define CONFIG_SYS_LOAD_ADDR 0x40010000
  82. #define CONFIG_SYS_CLK 80000000
  83. #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
  84. #define CONFIG_SYS_MBAR 0xFC000000
  85. /*
  86. * Low Level Configuration Settings
  87. * (address mappings, register initial values, etc.)
  88. * You should know what you are doing if you make changes here.
  89. */
  90. /*
  91. * Definitions for initial stack pointer and data area (in DPRAM)
  92. */
  93. #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
  94. #define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */
  95. #define CONFIG_SYS_INIT_RAM_CTRL 0x221
  96. #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
  97. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  98. /*
  99. * Start addresses for the final memory configuration
  100. * (Set up by the startup code)
  101. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  102. */
  103. #define CONFIG_SYS_SDRAM_BASE 0x40000000
  104. #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
  105. #define CONFIG_SYS_SDRAM_CFG1 0x43711630
  106. #define CONFIG_SYS_SDRAM_CFG2 0x56670000
  107. #define CONFIG_SYS_SDRAM_CTRL 0xE1092000
  108. #define CONFIG_SYS_SDRAM_EMOD 0x80010000
  109. #define CONFIG_SYS_SDRAM_MODE 0x00CD0000
  110. #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
  111. #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
  112. #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
  113. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  114. #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
  115. #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  116. /*
  117. * For booting Linux, the board info and command line data
  118. * have to be in the first 8 MB of memory, since this is
  119. * the maximum mapped by the Linux kernel during initialization ??
  120. */
  121. #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
  122. #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
  123. /*-----------------------------------------------------------------------
  124. * FLASH organization
  125. */
  126. #define CONFIG_SYS_FLASH_CFI
  127. #ifdef CONFIG_SYS_FLASH_CFI
  128. # define CONFIG_FLASH_CFI_DRIVER 1
  129. # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
  130. # define CONFIG_FLASH_SPANSION_S29WS_N 1
  131. # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
  132. # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  133. # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  134. # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
  135. # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
  136. #endif
  137. #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
  138. /* Configuration for environment
  139. * Environment is embedded in u-boot in the second sector of the flash
  140. */
  141. #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_BASE + 0x40000)
  142. #define CONFIG_ENV_SIZE 0x1000
  143. #define CONFIG_ENV_SECT_SIZE 0x8000
  144. #define LDS_BOARD_TEXT \
  145. . = DEFINED(env_offset) ? env_offset : .; \
  146. env/embedded.o(.text*)
  147. /*-----------------------------------------------------------------------
  148. * Cache Configuration
  149. */
  150. #define CONFIG_SYS_CACHELINE_SIZE 16
  151. #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  152. CONFIG_SYS_INIT_RAM_SIZE - 8)
  153. #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  154. CONFIG_SYS_INIT_RAM_SIZE - 4)
  155. #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
  156. #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
  157. CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
  158. CF_ACR_EN | CF_ACR_SM_ALL)
  159. #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
  160. CF_CACR_DCM_P)
  161. /*-----------------------------------------------------------------------
  162. * Chipselect bank definitions
  163. */
  164. /*
  165. * CS0 - NOR Flash
  166. * CS1 - Ext SRAM
  167. * CS2 - Available
  168. * CS3 - Available
  169. * CS4 - Available
  170. * CS5 - Available
  171. */
  172. #define CONFIG_SYS_CS0_BASE 0
  173. #define CONFIG_SYS_CS0_MASK 0x00FF0001
  174. #define CONFIG_SYS_CS0_CTRL 0x00001FA0
  175. #define CONFIG_SYS_CS1_BASE 0xC0000000
  176. #define CONFIG_SYS_CS1_MASK 0x00070001
  177. #define CONFIG_SYS_CS1_CTRL 0x00001FA0
  178. #endif /* _M53017EVB_H */