M5272C3.h 6.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuation settings for the Motorola MC5272C3 board.
  4. *
  5. * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
  6. */
  7. /*
  8. * board/config.h - configuration options, board specific
  9. */
  10. #ifndef _M5272C3_H
  11. #define _M5272C3_H
  12. /*
  13. * High Level Configuration Options
  14. * (easy to change)
  15. */
  16. #define CONFIG_MCFTMR
  17. #define CONFIG_MCFUART
  18. #define CONFIG_SYS_UART_PORT (0)
  19. #undef CONFIG_WATCHDOG
  20. #define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
  21. #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
  22. /* Configuration for environment
  23. * Environment is embedded in u-boot in the second sector of the flash
  24. */
  25. #ifndef CONFIG_MONITOR_IS_IN_RAM
  26. #define CONFIG_ENV_OFFSET 0x4000
  27. #define CONFIG_ENV_SECT_SIZE 0x2000
  28. #else
  29. #define CONFIG_ENV_ADDR 0xffe04000
  30. #define CONFIG_ENV_SECT_SIZE 0x2000
  31. #endif
  32. #define LDS_BOARD_TEXT \
  33. . = DEFINED(env_offset) ? env_offset : .; \
  34. env/embedded.o(.text);
  35. /*
  36. * BOOTP options
  37. */
  38. #define CONFIG_BOOTP_BOOTFILESIZE
  39. /*
  40. * Command line configuration.
  41. */
  42. #define CONFIG_MCFFEC
  43. #ifdef CONFIG_MCFFEC
  44. # define CONFIG_MII 1
  45. # define CONFIG_MII_INIT 1
  46. # define CONFIG_SYS_DISCOVER_PHY
  47. # define CONFIG_SYS_RX_ETH_BUFFER 8
  48. # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  49. # define CONFIG_SYS_FEC0_PINMUX 0
  50. # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
  51. # define MCFFEC_TOUT_LOOP 50000
  52. /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  53. # ifndef CONFIG_SYS_DISCOVER_PHY
  54. # define FECDUPLEX FULL
  55. # define FECSPEED _100BASET
  56. # else
  57. # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  58. # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  59. # endif
  60. # endif /* CONFIG_SYS_DISCOVER_PHY */
  61. #endif
  62. #ifdef CONFIG_MCFFEC
  63. # define CONFIG_IPADDR 192.162.1.2
  64. # define CONFIG_NETMASK 255.255.255.0
  65. # define CONFIG_SERVERIP 192.162.1.1
  66. # define CONFIG_GATEWAYIP 192.162.1.1
  67. #endif /* CONFIG_MCFFEC */
  68. #define CONFIG_HOSTNAME "M5272C3"
  69. #define CONFIG_EXTRA_ENV_SETTINGS \
  70. "netdev=eth0\0" \
  71. "loadaddr=10000\0" \
  72. "u-boot=u-boot.bin\0" \
  73. "load=tftp ${loadaddr) ${u-boot}\0" \
  74. "upd=run load; run prog\0" \
  75. "prog=prot off ffe00000 ffe3ffff;" \
  76. "era ffe00000 ffe3ffff;" \
  77. "cp.b ${loadaddr} ffe00000 ${filesize};"\
  78. "save\0" \
  79. ""
  80. #define CONFIG_SYS_LOAD_ADDR 0x20000
  81. #define CONFIG_SYS_MEMTEST_START 0x400
  82. #define CONFIG_SYS_MEMTEST_END 0x380000
  83. #define CONFIG_SYS_CLK 66000000
  84. /*
  85. * Low Level Configuration Settings
  86. * (address mappings, register initial values, etc.)
  87. * You should know what you are doing if you make changes here.
  88. */
  89. #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
  90. #define CONFIG_SYS_SCR 0x0003
  91. #define CONFIG_SYS_SPR 0xffff
  92. /*-----------------------------------------------------------------------
  93. * Definitions for initial stack pointer and data area (in DPRAM)
  94. */
  95. #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
  96. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
  97. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  98. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  99. /*-----------------------------------------------------------------------
  100. * Start addresses for the final memory configuration
  101. * (Set up by the startup code)
  102. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  103. */
  104. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  105. #define CONFIG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */
  106. #define CONFIG_SYS_FLASH_BASE 0xffe00000
  107. #ifdef CONFIG_MONITOR_IS_IN_RAM
  108. #define CONFIG_SYS_MONITOR_BASE 0x20000
  109. #else
  110. #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
  111. #endif
  112. #define CONFIG_SYS_MONITOR_LEN 0x20000
  113. #define CONFIG_SYS_MALLOC_LEN (256 << 10)
  114. #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
  115. /*
  116. * For booting Linux, the board info and command line data
  117. * have to be in the first 8 MB of memory, since this is
  118. * the maximum mapped by the Linux kernel during initialization ??
  119. */
  120. #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
  121. /*
  122. * FLASH organization
  123. */
  124. #define CONFIG_SYS_FLASH_CFI
  125. #ifdef CONFIG_SYS_FLASH_CFI
  126. # define CONFIG_FLASH_CFI_DRIVER 1
  127. # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
  128. # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  129. # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  130. # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
  131. # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
  132. #endif
  133. /*-----------------------------------------------------------------------
  134. * Cache Configuration
  135. */
  136. #define CONFIG_SYS_CACHELINE_SIZE 16
  137. #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  138. CONFIG_SYS_INIT_RAM_SIZE - 8)
  139. #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  140. CONFIG_SYS_INIT_RAM_SIZE - 4)
  141. #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
  142. #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
  143. CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
  144. CF_ACR_EN | CF_ACR_SM_ALL)
  145. #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
  146. CF_CACR_DISD | CF_CACR_INVI | \
  147. CF_CACR_CEIB | CF_CACR_DCM | \
  148. CF_CACR_EUSP)
  149. /*-----------------------------------------------------------------------
  150. * Memory bank definitions
  151. */
  152. #define CONFIG_SYS_BR0_PRELIM 0xFFE00201
  153. #define CONFIG_SYS_OR0_PRELIM 0xFFE00014
  154. #define CONFIG_SYS_BR1_PRELIM 0
  155. #define CONFIG_SYS_OR1_PRELIM 0
  156. #define CONFIG_SYS_BR2_PRELIM 0x30000001
  157. #define CONFIG_SYS_OR2_PRELIM 0xFFF80000
  158. #define CONFIG_SYS_BR3_PRELIM 0
  159. #define CONFIG_SYS_OR3_PRELIM 0
  160. #define CONFIG_SYS_BR4_PRELIM 0
  161. #define CONFIG_SYS_OR4_PRELIM 0
  162. #define CONFIG_SYS_BR5_PRELIM 0
  163. #define CONFIG_SYS_OR5_PRELIM 0
  164. #define CONFIG_SYS_BR6_PRELIM 0
  165. #define CONFIG_SYS_OR6_PRELIM 0
  166. #define CONFIG_SYS_BR7_PRELIM 0x00000701
  167. #define CONFIG_SYS_OR7_PRELIM 0xFFC0007C
  168. /*-----------------------------------------------------------------------
  169. * Port configuration
  170. */
  171. #define CONFIG_SYS_PACNT 0x00000000
  172. #define CONFIG_SYS_PADDR 0x0000
  173. #define CONFIG_SYS_PADAT 0x0000
  174. #define CONFIG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */
  175. #define CONFIG_SYS_PBDDR 0x0000
  176. #define CONFIG_SYS_PBDAT 0x0000
  177. #define CONFIG_SYS_PDCNT 0x00000000
  178. #endif /* _M5272C3_H */