M5253DEMO.h 6.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  3. * Hayden Fraser (Hayden.Fraser@freescale.com)
  4. */
  5. #ifndef _M5253DEMO_H
  6. #define _M5253DEMO_H
  7. #define CONFIG_MCFTMR
  8. #define CONFIG_MCFUART
  9. #define CONFIG_SYS_UART_PORT (0)
  10. #undef CONFIG_WATCHDOG /* disable watchdog */
  11. /* Configuration for environment
  12. * Environment is embedded in u-boot in the second sector of the flash
  13. */
  14. #ifdef CONFIG_MONITOR_IS_IN_RAM
  15. # define CONFIG_ENV_OFFSET 0x4000
  16. # define CONFIG_ENV_SECT_SIZE 0x1000
  17. #else
  18. # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
  19. # define CONFIG_ENV_SECT_SIZE 0x1000
  20. #endif
  21. #define LDS_BOARD_TEXT \
  22. . = DEFINED(env_offset) ? env_offset : .; \
  23. env/embedded.o(.text*);
  24. /*
  25. * Command line configuration.
  26. */
  27. #ifdef CONFIG_IDE
  28. /* ATA */
  29. # define CONFIG_IDE_RESET 1
  30. # define CONFIG_IDE_PREINIT 1
  31. # define CONFIG_ATAPI
  32. # undef CONFIG_LBA48
  33. # define CONFIG_SYS_IDE_MAXBUS 1
  34. # define CONFIG_SYS_IDE_MAXDEVICE 2
  35. # define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
  36. # define CONFIG_SYS_ATA_IDE0_OFFSET 0
  37. # define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
  38. # define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
  39. # define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
  40. # define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
  41. #endif
  42. #define CONFIG_DRIVER_DM9000
  43. #ifdef CONFIG_DRIVER_DM9000
  44. # define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300)
  45. # define DM9000_IO CONFIG_DM9000_BASE
  46. # define DM9000_DATA (CONFIG_DM9000_BASE + 4)
  47. # undef CONFIG_DM9000_DEBUG
  48. # define CONFIG_DM9000_BYTE_SWAPPED
  49. # define CONFIG_OVERWRITE_ETHADDR_ONCE
  50. # define CONFIG_EXTRA_ENV_SETTINGS \
  51. "netdev=eth0\0" \
  52. "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
  53. "loadaddr=10000\0" \
  54. "u-boot=u-boot.bin\0" \
  55. "load=tftp ${loadaddr) ${u-boot}\0" \
  56. "upd=run load; run prog\0" \
  57. "prog=prot off 0xff800000 0xff82ffff;" \
  58. "era 0xff800000 0xff82ffff;" \
  59. "cp.b ${loadaddr} 0xff800000 ${filesize};" \
  60. "save\0" \
  61. ""
  62. #endif
  63. #define CONFIG_HOSTNAME "M5253DEMO"
  64. /* I2C */
  65. #define CONFIG_SYS_I2C
  66. #define CONFIG_SYS_I2C_FSL
  67. #define CONFIG_SYS_FSL_I2C_SPEED 80000
  68. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  69. #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280
  70. #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
  71. #define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
  72. #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
  73. #define CONFIG_SYS_I2C_PINMUX_SET (0)
  74. #define CONFIG_SYS_LOAD_ADDR 0x00100000
  75. #define CONFIG_SYS_MEMTEST_START 0x400
  76. #define CONFIG_SYS_MEMTEST_END 0x380000
  77. #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
  78. #define CONFIG_SYS_FAST_CLK
  79. #ifdef CONFIG_SYS_FAST_CLK
  80. # define CONFIG_SYS_PLLCR 0x1243E054
  81. # define CONFIG_SYS_CLK 140000000
  82. #else
  83. # define CONFIG_SYS_PLLCR 0x135a4140
  84. # define CONFIG_SYS_CLK 70000000
  85. #endif
  86. /*
  87. * Low Level Configuration Settings
  88. * (address mappings, register initial values, etc.)
  89. * You should know what you are doing if you make changes here.
  90. */
  91. #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
  92. #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
  93. /*
  94. * Definitions for initial stack pointer and data area (in DPRAM)
  95. */
  96. #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
  97. #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
  98. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  99. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  100. /*
  101. * Start addresses for the final memory configuration
  102. * (Set up by the startup code)
  103. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  104. */
  105. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  106. #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
  107. #ifdef CONFIG_MONITOR_IS_IN_RAM
  108. # define CONFIG_SYS_MONITOR_BASE 0x20000
  109. #else
  110. # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
  111. #endif
  112. #define CONFIG_SYS_MONITOR_LEN 0x40000
  113. #define CONFIG_SYS_MALLOC_LEN (256 << 10)
  114. #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
  115. /*
  116. * For booting Linux, the board info and command line data
  117. * have to be in the first 8 MB of memory, since this is
  118. * the maximum mapped by the Linux kernel during initialization ??
  119. */
  120. #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
  121. #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
  122. /* FLASH organization */
  123. #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
  124. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  125. #define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */
  126. #define CONFIG_SYS_FLASH_ERASE_TOUT 1000
  127. #define FLASH_SST6401B 0x200
  128. #define SST_ID_xF6401B 0x236D236D
  129. #undef CONFIG_SYS_FLASH_CFI
  130. #ifdef CONFIG_SYS_FLASH_CFI
  131. /*
  132. * Unable to use CFI driver, due to incompatible sector erase command by SST.
  133. * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
  134. * 0x30 is block erase in SST
  135. */
  136. # define CONFIG_FLASH_CFI_DRIVER 1
  137. # define CONFIG_SYS_FLASH_SIZE 0x800000
  138. # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  139. # define CONFIG_FLASH_CFI_LEGACY
  140. #else
  141. # define CONFIG_SYS_SST_SECT 2048
  142. # define CONFIG_SYS_SST_SECTSZ 0x1000
  143. # define CONFIG_SYS_FLASH_WRITE_TOUT 500
  144. #endif
  145. /* Cache Configuration */
  146. #define CONFIG_SYS_CACHELINE_SIZE 16
  147. #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  148. CONFIG_SYS_INIT_RAM_SIZE - 8)
  149. #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  150. CONFIG_SYS_INIT_RAM_SIZE - 4)
  151. #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
  152. #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
  153. CF_ADDRMASK(8) | \
  154. CF_ACR_EN | CF_ACR_SM_ALL)
  155. #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
  156. CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
  157. CF_ACR_EN | CF_ACR_SM_ALL)
  158. #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
  159. CF_CACR_DBWE)
  160. /* Port configuration */
  161. #define CONFIG_SYS_FECI2C 0xF0
  162. #define CONFIG_SYS_CS0_BASE 0xFF800000
  163. #define CONFIG_SYS_CS0_MASK 0x007F0021
  164. #define CONFIG_SYS_CS0_CTRL 0x00001D80
  165. #define CONFIG_SYS_CS1_BASE 0xE0000000
  166. #define CONFIG_SYS_CS1_MASK 0x00000001
  167. #define CONFIG_SYS_CS1_CTRL 0x00003DD8
  168. /*-----------------------------------------------------------------------
  169. * Port configuration
  170. */
  171. #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
  172. #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
  173. #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
  174. #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
  175. #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
  176. #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
  177. #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
  178. #endif /* _M5253DEMO_H */