M52277EVB.h 8.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuation settings for the Freescale MCF52277 EVB board.
  4. *
  5. * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  6. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  7. */
  8. /*
  9. * board/config.h - configuration options, board specific
  10. */
  11. #ifndef _M52277EVB_H
  12. #define _M52277EVB_H
  13. /*
  14. * High Level Configuration Options
  15. * (easy to change)
  16. */
  17. #define CONFIG_MCFUART
  18. #define CONFIG_SYS_UART_PORT (0)
  19. #undef CONFIG_WATCHDOG
  20. #define CONFIG_TIMESTAMP /* Print image info with timestamp */
  21. /*
  22. * BOOTP options
  23. */
  24. #define CONFIG_BOOTP_BOOTFILESIZE
  25. #define CONFIG_HOSTNAME "M52277EVB"
  26. #define CONFIG_SYS_UBOOT_END 0x3FFFF
  27. #define CONFIG_SYS_LOAD_ADDR2 0x40010007
  28. #ifdef CONFIG_SYS_STMICRO_BOOT
  29. /* ST Micro serial flash */
  30. #define CONFIG_EXTRA_ENV_SETTINGS \
  31. "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
  32. "loadaddr=0x40010000\0" \
  33. "uboot=u-boot.bin\0" \
  34. "load=loadb ${loadaddr} ${baudrate};" \
  35. "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
  36. "upd=run load; run prog\0" \
  37. "prog=sf probe 0:2 10000 1;" \
  38. "sf erase 0 30000;" \
  39. "sf write ${loadaddr} 0 30000;" \
  40. "save\0" \
  41. ""
  42. #endif
  43. #ifdef CONFIG_SYS_SPANSION_BOOT
  44. #define CONFIG_EXTRA_ENV_SETTINGS \
  45. "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
  46. "loadaddr=0x40010000\0" \
  47. "uboot=u-boot.bin\0" \
  48. "load=loadb ${loadaddr} ${baudrate}\0" \
  49. "upd=run load; run prog\0" \
  50. "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \
  51. " " __stringify(CONFIG_SYS_UBOOT_END) ";" \
  52. "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \
  53. __stringify(CONFIG_SYS_UBOOT_END) ";" \
  54. "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \
  55. " ${filesize}; save\0" \
  56. "updsbf=run loadsbf; run progsbf\0" \
  57. "loadsbf=loadb ${loadaddr} ${baudrate};" \
  58. "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
  59. "progsbf=sf probe 0:2 10000 1;" \
  60. "sf erase 0 30000;" \
  61. "sf write ${loadaddr} 0 30000;" \
  62. ""
  63. #endif
  64. /* LCD */
  65. #ifdef CONFIG_CMD_BMP
  66. #define CONFIG_SPLASH_SCREEN
  67. #define CONFIG_LCD_LOGO
  68. #define CONFIG_SHARP_LQ035Q7DH06
  69. #endif
  70. /* USB */
  71. #ifdef CONFIG_CMD_USB
  72. #define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000
  73. #define CONFIG_SYS_USB_EHCI_CPU_INIT
  74. #endif
  75. /* Realtime clock */
  76. #define CONFIG_MCFRTC
  77. #undef RTC_DEBUG
  78. #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
  79. /* Timer */
  80. #define CONFIG_MCFTMR
  81. #undef CONFIG_MCFPIT
  82. /* I2c */
  83. #define CONFIG_SYS_I2C
  84. #define CONFIG_SYS_I2C_FSL
  85. #define CONFIG_SYS_FSL_I2C_SPEED 80000
  86. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  87. #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
  88. #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
  89. /* DSPI and Serial Flash */
  90. #define CONFIG_CF_DSPI
  91. #define CONFIG_HARD_SPI
  92. #define CONFIG_SYS_SBFHDR_SIZE 0x7
  93. #ifdef CONFIG_CMD_SPI
  94. # define CONFIG_SYS_DSPI_CS2
  95. # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
  96. DSPI_CTAR_PCSSCK_1CLK | \
  97. DSPI_CTAR_PASC(0) | \
  98. DSPI_CTAR_PDT(0) | \
  99. DSPI_CTAR_CSSCK(0) | \
  100. DSPI_CTAR_ASC(0) | \
  101. DSPI_CTAR_DT(1))
  102. #endif
  103. /* Input, PCI, Flexbus, and VCO */
  104. #define CONFIG_EXTRA_CLOCK
  105. #define CONFIG_SYS_INPUT_CLKSRC 16000000
  106. #define CONFIG_PRAM 2048 /* 2048 KB */
  107. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
  108. #define CONFIG_SYS_MBAR 0xFC000000
  109. /*
  110. * Low Level Configuration Settings
  111. * (address mappings, register initial values, etc.)
  112. * You should know what you are doing if you make changes here.
  113. */
  114. /*
  115. * Definitions for initial stack pointer and data area (in DPRAM)
  116. */
  117. #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
  118. #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
  119. #define CONFIG_SYS_INIT_RAM_CTRL 0x221
  120. #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
  121. #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32)
  122. #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
  123. /*
  124. * Start addresses for the final memory configuration
  125. * (Set up by the startup code)
  126. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  127. */
  128. #define CONFIG_SYS_SDRAM_BASE 0x40000000
  129. #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
  130. #define CONFIG_SYS_SDRAM_CFG1 0x43711630
  131. #define CONFIG_SYS_SDRAM_CFG2 0x56670000
  132. #define CONFIG_SYS_SDRAM_CTRL 0xE1092000
  133. #define CONFIG_SYS_SDRAM_EMOD 0x81810000
  134. #define CONFIG_SYS_SDRAM_MODE 0x00CD0000
  135. #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00
  136. #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
  137. #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
  138. #ifdef CONFIG_CF_SBF
  139. # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
  140. #else
  141. # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
  142. #endif
  143. #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
  144. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  145. #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  146. /* Initial Memory map for Linux */
  147. #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
  148. #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
  149. /*
  150. * Configuration for environment
  151. * Environment is not embedded in u-boot. First time runing may have env
  152. * crc error warning if there is no correct environment on the flash.
  153. */
  154. #ifdef CONFIG_CF_SBF
  155. # define CONFIG_ENV_SPI_CS 2
  156. #endif
  157. #define CONFIG_ENV_OVERWRITE 1
  158. /*-----------------------------------------------------------------------
  159. * FLASH organization
  160. */
  161. #ifdef CONFIG_SYS_STMICRO_BOOT
  162. # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
  163. # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
  164. # define CONFIG_ENV_OFFSET 0x30000
  165. # define CONFIG_ENV_SIZE 0x1000
  166. # define CONFIG_ENV_SECT_SIZE 0x10000
  167. #endif
  168. #ifdef CONFIG_SYS_SPANSION_BOOT
  169. # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
  170. # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
  171. # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
  172. # define CONFIG_ENV_SIZE 0x1000
  173. # define CONFIG_ENV_SECT_SIZE 0x8000
  174. #endif
  175. #define CONFIG_SYS_FLASH_CFI
  176. #ifdef CONFIG_SYS_FLASH_CFI
  177. # define CONFIG_FLASH_CFI_DRIVER 1
  178. # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
  179. # define CONFIG_FLASH_SPANSION_S29WS_N 1
  180. # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
  181. # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  182. # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  183. # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
  184. # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
  185. # define CONFIG_SYS_FLASH_CHECKSUM
  186. # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
  187. #endif
  188. #define LDS_BOARD_TEXT \
  189. arch/m68k/cpu/mcf5227x/built-in.o (.text*) \
  190. arch/m68k/lib/built-in.o (.text*)
  191. /*
  192. * This is setting for JFFS2 support in u-boot.
  193. * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
  194. */
  195. #ifdef CONFIG_CMD_JFFS2
  196. # define CONFIG_JFFS2_DEV "nor0"
  197. # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x40000)
  198. # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000)
  199. #endif
  200. /*-----------------------------------------------------------------------
  201. * Cache Configuration
  202. */
  203. #define CONFIG_SYS_CACHELINE_SIZE 16
  204. #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  205. CONFIG_SYS_INIT_RAM_SIZE - 8)
  206. #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  207. CONFIG_SYS_INIT_RAM_SIZE - 4)
  208. #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
  209. #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
  210. CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
  211. CF_ACR_EN | CF_ACR_SM_ALL)
  212. #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
  213. CF_CACR_DISD | CF_CACR_INVI | \
  214. CF_CACR_CEIB | CF_CACR_DCM | \
  215. CF_CACR_EUSP)
  216. /*-----------------------------------------------------------------------
  217. * Memory bank definitions
  218. */
  219. /*
  220. * CS0 - NOR Flash
  221. * CS1 - Available
  222. * CS2 - Available
  223. * CS3 - Available
  224. * CS4 - Available
  225. * CS5 - Available
  226. */
  227. #ifdef CONFIG_CF_SBF
  228. #define CONFIG_SYS_CS0_BASE 0x04000000
  229. #define CONFIG_SYS_CS0_MASK 0x00FF0001
  230. #define CONFIG_SYS_CS0_CTRL 0x00001FA0
  231. #else
  232. #define CONFIG_SYS_CS0_BASE 0x00000000
  233. #define CONFIG_SYS_CS0_MASK 0x00FF0001
  234. #define CONFIG_SYS_CS0_CTRL 0x00001FA0
  235. #endif
  236. #endif /* _M52277EVB_H */