bmips_ram.c 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
  4. *
  5. * Derived from linux/arch/mips/bcm63xx/cpu.c:
  6. * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
  7. * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <errno.h>
  12. #include <ram.h>
  13. #include <asm/io.h>
  14. #define SDRAM_CFG_REG 0x0
  15. #define SDRAM_CFG_COL_SHIFT 4
  16. #define SDRAM_CFG_COL_MASK (0x3 << SDRAM_CFG_COL_SHIFT)
  17. #define SDRAM_CFG_ROW_SHIFT 6
  18. #define SDRAM_CFG_ROW_MASK (0x3 << SDRAM_CFG_ROW_SHIFT)
  19. #define SDRAM_CFG_32B_SHIFT 10
  20. #define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT)
  21. #define SDRAM_CFG_BANK_SHIFT 13
  22. #define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
  23. #define SDRAM_6318_SPACE_SHIFT 4
  24. #define SDRAM_6318_SPACE_MASK (0xf << SDRAM_6318_SPACE_SHIFT)
  25. #define MEMC_CFG_REG 0x4
  26. #define MEMC_CFG_32B_SHIFT 1
  27. #define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT)
  28. #define MEMC_CFG_COL_SHIFT 3
  29. #define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT)
  30. #define MEMC_CFG_ROW_SHIFT 6
  31. #define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT)
  32. #define DDR_CSEND_REG 0x8
  33. struct bmips_ram_priv;
  34. struct bmips_ram_hw {
  35. ulong (*get_ram_size)(struct bmips_ram_priv *);
  36. };
  37. struct bmips_ram_priv {
  38. void __iomem *regs;
  39. const struct bmips_ram_hw *hw;
  40. };
  41. static ulong bcm6318_get_ram_size(struct bmips_ram_priv *priv)
  42. {
  43. u32 val;
  44. val = readl_be(priv->regs + SDRAM_CFG_REG);
  45. val = (val & SDRAM_6318_SPACE_MASK) >> SDRAM_6318_SPACE_SHIFT;
  46. return (1 << (val + 20));
  47. }
  48. static ulong bcm6328_get_ram_size(struct bmips_ram_priv *priv)
  49. {
  50. return readl_be(priv->regs + DDR_CSEND_REG) << 24;
  51. }
  52. static ulong bmips_dram_size(unsigned int cols, unsigned int rows,
  53. unsigned int is_32b, unsigned int banks)
  54. {
  55. rows += 11; /* 0 => 11 address bits ... 2 => 13 address bits */
  56. cols += 8; /* 0 => 8 address bits ... 2 => 10 address bits */
  57. is_32b += 1;
  58. return 1 << (cols + rows + is_32b + banks);
  59. }
  60. static ulong bcm6338_get_ram_size(struct bmips_ram_priv *priv)
  61. {
  62. unsigned int cols = 0, rows = 0, is_32b = 0, banks = 0;
  63. u32 val;
  64. val = readl_be(priv->regs + SDRAM_CFG_REG);
  65. rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
  66. cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
  67. is_32b = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
  68. banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
  69. return bmips_dram_size(cols, rows, is_32b, banks);
  70. }
  71. static ulong bcm6358_get_ram_size(struct bmips_ram_priv *priv)
  72. {
  73. unsigned int cols = 0, rows = 0, is_32b = 0;
  74. u32 val;
  75. val = readl_be(priv->regs + MEMC_CFG_REG);
  76. rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
  77. cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
  78. is_32b = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
  79. return bmips_dram_size(cols, rows, is_32b, 2);
  80. }
  81. static int bmips_ram_get_info(struct udevice *dev, struct ram_info *info)
  82. {
  83. struct bmips_ram_priv *priv = dev_get_priv(dev);
  84. const struct bmips_ram_hw *hw = priv->hw;
  85. info->base = 0x80000000;
  86. info->size = hw->get_ram_size(priv);
  87. return 0;
  88. }
  89. static const struct ram_ops bmips_ram_ops = {
  90. .get_info = bmips_ram_get_info,
  91. };
  92. static const struct bmips_ram_hw bmips_ram_bcm6318 = {
  93. .get_ram_size = bcm6318_get_ram_size,
  94. };
  95. static const struct bmips_ram_hw bmips_ram_bcm6328 = {
  96. .get_ram_size = bcm6328_get_ram_size,
  97. };
  98. static const struct bmips_ram_hw bmips_ram_bcm6338 = {
  99. .get_ram_size = bcm6338_get_ram_size,
  100. };
  101. static const struct bmips_ram_hw bmips_ram_bcm6358 = {
  102. .get_ram_size = bcm6358_get_ram_size,
  103. };
  104. static const struct udevice_id bmips_ram_ids[] = {
  105. {
  106. .compatible = "brcm,bcm6318-mc",
  107. .data = (ulong)&bmips_ram_bcm6318,
  108. }, {
  109. .compatible = "brcm,bcm6328-mc",
  110. .data = (ulong)&bmips_ram_bcm6328,
  111. }, {
  112. .compatible = "brcm,bcm6338-mc",
  113. .data = (ulong)&bmips_ram_bcm6338,
  114. }, {
  115. .compatible = "brcm,bcm6358-mc",
  116. .data = (ulong)&bmips_ram_bcm6358,
  117. }, { /* sentinel */ }
  118. };
  119. static int bmips_ram_probe(struct udevice *dev)
  120. {
  121. struct bmips_ram_priv *priv = dev_get_priv(dev);
  122. const struct bmips_ram_hw *hw =
  123. (const struct bmips_ram_hw *)dev_get_driver_data(dev);
  124. fdt_addr_t addr;
  125. fdt_size_t size;
  126. addr = devfdt_get_addr_size_index(dev, 0, &size);
  127. if (addr == FDT_ADDR_T_NONE)
  128. return -EINVAL;
  129. priv->regs = ioremap(addr, size);
  130. priv->hw = hw;
  131. return 0;
  132. }
  133. U_BOOT_DRIVER(bmips_ram) = {
  134. .name = "bmips-mc",
  135. .id = UCLASS_RAM,
  136. .of_match = bmips_ram_ids,
  137. .probe = bmips_ram_probe,
  138. .priv_auto_alloc_size = sizeof(struct bmips_ram_priv),
  139. .ops = &bmips_ram_ops,
  140. .flags = DM_FLAG_PRE_RELOC,
  141. };