README.xtensa 4.3 KB

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  1. U-Boot for the Xtensa Architecture
  2. ==================================
  3. Xtensa Architecture and Diamond Cores
  4. -------------------------------------
  5. Xtensa is a configurable processor architecture from Tensilica, Inc.
  6. Diamond Cores are pre-configured instances available for license and
  7. SoC cores in the same manner as ARM, MIPS, etc.
  8. Xtensa licensees create their own Xtensa cores with selected features
  9. and custom instructions, registers and co-processors. The custom core
  10. is configured with Tensilica tools and built with Tensilica's Xtensa
  11. Processor Generator.
  12. There are an effectively infinite number of CPUs in the Xtensa
  13. architecture family. It is, however, not feasible to support individual
  14. Xtensa CPUs in U-Boot. Therefore, there is only a single 'xtensa' CPU
  15. in the cpu tree of U-Boot.
  16. In the same manner as the Linux port to Xtensa, U-Boot adapts to an
  17. individual Xtensa core configuration using a set of macros provided with
  18. the particular core. This is part of what is known as the hardware
  19. abstraction layer (HAL). For the purpose of U-Boot, the HAL consists only
  20. of a few header files. These provide CPP macros that customize sources,
  21. Makefiles, and the linker script.
  22. Adding support for an additional processor configuration
  23. --------------------------------------------------------
  24. The header files for one particular processor configuration are inside
  25. a variant-specific directory located in the arch/xtensa/include/asm
  26. directory. The name of that directory starts with 'arch-' followed by
  27. the name for the processor configuration, for example, arch-dc233c for
  28. the Diamond DC233 processor.
  29. core.h Definitions for the core itself.
  30. The following files are part of the overlay but not used by U-Boot.
  31. tie.h Co-processors and custom extensions defined
  32. in the Tensilica Instruction Extension (TIE)
  33. language.
  34. tie-asm.h Assembly macros to access custom-defined registers
  35. and states.
  36. Global Data Pointer, Exported Function Stubs, and the ABI
  37. ---------------------------------------------------------
  38. To support standalone applications launched with the "go" command,
  39. U-Boot provides a jump table of entrypoints to exported functions
  40. (grep for EXPORT_FUNC). The implementation for Xtensa depends on
  41. which ABI (or function calling convention) is used.
  42. Windowed ABI presents unique difficulties with the approach based on
  43. keeping global data pointer in dedicated register. Because the register
  44. window rotates during a call, there is no register that is constantly
  45. available for the gd pointer. Therefore, on xtensa gd is a simple
  46. global variable. Another difficulty arises from the requirement to have
  47. an 'entry' at the beginning of a function, which rotates the register
  48. file and reserves a stack frame. This is an integral part of the
  49. windowed ABI implemented in hardware. It makes using a jump table to an
  50. arbitrary (separately compiled) function a bit tricky. Use of a simple
  51. wrapper is also very tedious due to the need to move all possible
  52. register arguments and adjust the stack to handle arguments that cannot
  53. be passed in registers. The most efficient approach is to have the jump
  54. table perform the 'entry' so as to pretend it's the start of the real
  55. function. This requires decoding the target function's 'entry'
  56. instruction to determine the stack frame size, and adjusting the stack
  57. pointer accordingly, then jumping into the target function just after
  58. the 'entry'. Decoding depends on the processor's endianness so uses the
  59. HAL. The implementation (12 instructions) is in examples/stubs.c.
  60. Access to Invalid Memory Addresses
  61. ----------------------------------
  62. U-Boot does not check if memory addresses given as arguments to commands
  63. such as "md" are valid. There are two possible types of invalid
  64. addresses: an area of physical address space may not be mapped to RAM
  65. or peripherals, or in the presence of MMU an area of virtual address
  66. space may not be mapped to physical addresses.
  67. Accessing first type of invalid addresses may result in hardware lockup,
  68. reading of meaningless data, written data being ignored or an exception,
  69. depending on the CPU wiring to the system. Accessing second type of
  70. invalid addresses always ends with an exception.
  71. U-Boot for Xtensa provides a special memory exception handler that
  72. reports such access attempts and resets the board.
  73. ------------------------------------------------------------------------------
  74. Chris Zankel
  75. Ross Morley