fsmc_nand.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2010
  4. * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com.
  5. *
  6. * (C) Copyright 2012
  7. * Amit Virdi, ST Microelectronics, amit.virdi@st.com.
  8. */
  9. #include <common.h>
  10. #include <nand.h>
  11. #include <asm/io.h>
  12. #include <linux/bitops.h>
  13. #include <linux/err.h>
  14. #include <linux/mtd/nand_ecc.h>
  15. #include <linux/mtd/fsmc_nand.h>
  16. #include <asm/arch/hardware.h>
  17. static u32 fsmc_version;
  18. static struct fsmc_regs *const fsmc_regs_p = (struct fsmc_regs *)
  19. CONFIG_SYS_FSMC_BASE;
  20. /*
  21. * ECC4 and ECC1 have 13 bytes and 3 bytes of ecc respectively for 512 bytes of
  22. * data. ECC4 can correct up to 8 bits in 512 bytes of data while ECC1 can
  23. * correct 1 bit in 512 bytes
  24. */
  25. static struct nand_ecclayout fsmc_ecc4_lp_layout = {
  26. .eccbytes = 104,
  27. .eccpos = { 2, 3, 4, 5, 6, 7, 8,
  28. 9, 10, 11, 12, 13, 14,
  29. 18, 19, 20, 21, 22, 23, 24,
  30. 25, 26, 27, 28, 29, 30,
  31. 34, 35, 36, 37, 38, 39, 40,
  32. 41, 42, 43, 44, 45, 46,
  33. 50, 51, 52, 53, 54, 55, 56,
  34. 57, 58, 59, 60, 61, 62,
  35. 66, 67, 68, 69, 70, 71, 72,
  36. 73, 74, 75, 76, 77, 78,
  37. 82, 83, 84, 85, 86, 87, 88,
  38. 89, 90, 91, 92, 93, 94,
  39. 98, 99, 100, 101, 102, 103, 104,
  40. 105, 106, 107, 108, 109, 110,
  41. 114, 115, 116, 117, 118, 119, 120,
  42. 121, 122, 123, 124, 125, 126
  43. },
  44. .oobfree = {
  45. {.offset = 15, .length = 3},
  46. {.offset = 31, .length = 3},
  47. {.offset = 47, .length = 3},
  48. {.offset = 63, .length = 3},
  49. {.offset = 79, .length = 3},
  50. {.offset = 95, .length = 3},
  51. {.offset = 111, .length = 3},
  52. {.offset = 127, .length = 1}
  53. }
  54. };
  55. /*
  56. * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 224 bytes. 13*8 bytes
  57. * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 118
  58. * bytes are free for use.
  59. */
  60. static struct nand_ecclayout fsmc_ecc4_224_layout = {
  61. .eccbytes = 104,
  62. .eccpos = { 2, 3, 4, 5, 6, 7, 8,
  63. 9, 10, 11, 12, 13, 14,
  64. 18, 19, 20, 21, 22, 23, 24,
  65. 25, 26, 27, 28, 29, 30,
  66. 34, 35, 36, 37, 38, 39, 40,
  67. 41, 42, 43, 44, 45, 46,
  68. 50, 51, 52, 53, 54, 55, 56,
  69. 57, 58, 59, 60, 61, 62,
  70. 66, 67, 68, 69, 70, 71, 72,
  71. 73, 74, 75, 76, 77, 78,
  72. 82, 83, 84, 85, 86, 87, 88,
  73. 89, 90, 91, 92, 93, 94,
  74. 98, 99, 100, 101, 102, 103, 104,
  75. 105, 106, 107, 108, 109, 110,
  76. 114, 115, 116, 117, 118, 119, 120,
  77. 121, 122, 123, 124, 125, 126
  78. },
  79. .oobfree = {
  80. {.offset = 15, .length = 3},
  81. {.offset = 31, .length = 3},
  82. {.offset = 47, .length = 3},
  83. {.offset = 63, .length = 3},
  84. {.offset = 79, .length = 3},
  85. {.offset = 95, .length = 3},
  86. {.offset = 111, .length = 3},
  87. {.offset = 127, .length = 97}
  88. }
  89. };
  90. /*
  91. * ECC placement definitions in oobfree type format
  92. * There are 13 bytes of ecc for every 512 byte block and it has to be read
  93. * consecutively and immediately after the 512 byte data block for hardware to
  94. * generate the error bit offsets in 512 byte data
  95. * Managing the ecc bytes in the following way makes it easier for software to
  96. * read ecc bytes consecutive to data bytes. This way is similar to
  97. * oobfree structure maintained already in u-boot nand driver
  98. */
  99. static struct fsmc_eccplace fsmc_eccpl_lp = {
  100. .eccplace = {
  101. {.offset = 2, .length = 13},
  102. {.offset = 18, .length = 13},
  103. {.offset = 34, .length = 13},
  104. {.offset = 50, .length = 13},
  105. {.offset = 66, .length = 13},
  106. {.offset = 82, .length = 13},
  107. {.offset = 98, .length = 13},
  108. {.offset = 114, .length = 13}
  109. }
  110. };
  111. static struct nand_ecclayout fsmc_ecc4_sp_layout = {
  112. .eccbytes = 13,
  113. .eccpos = { 0, 1, 2, 3, 6, 7, 8,
  114. 9, 10, 11, 12, 13, 14
  115. },
  116. .oobfree = {
  117. {.offset = 15, .length = 1},
  118. }
  119. };
  120. static struct fsmc_eccplace fsmc_eccpl_sp = {
  121. .eccplace = {
  122. {.offset = 0, .length = 4},
  123. {.offset = 6, .length = 9}
  124. }
  125. };
  126. static struct nand_ecclayout fsmc_ecc1_layout = {
  127. .eccbytes = 24,
  128. .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52,
  129. 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116},
  130. .oobfree = {
  131. {.offset = 8, .length = 8},
  132. {.offset = 24, .length = 8},
  133. {.offset = 40, .length = 8},
  134. {.offset = 56, .length = 8},
  135. {.offset = 72, .length = 8},
  136. {.offset = 88, .length = 8},
  137. {.offset = 104, .length = 8},
  138. {.offset = 120, .length = 8}
  139. }
  140. };
  141. /* Count the number of 0's in buff upto a max of max_bits */
  142. static int count_written_bits(uint8_t *buff, int size, int max_bits)
  143. {
  144. int k, written_bits = 0;
  145. for (k = 0; k < size; k++) {
  146. written_bits += hweight8(~buff[k]);
  147. if (written_bits > max_bits)
  148. break;
  149. }
  150. return written_bits;
  151. }
  152. static void fsmc_nand_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl)
  153. {
  154. struct nand_chip *this = mtd_to_nand(mtd);
  155. ulong IO_ADDR_W;
  156. if (ctrl & NAND_CTRL_CHANGE) {
  157. IO_ADDR_W = (ulong)this->IO_ADDR_W;
  158. IO_ADDR_W &= ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE);
  159. if (ctrl & NAND_CLE)
  160. IO_ADDR_W |= CONFIG_SYS_NAND_CLE;
  161. if (ctrl & NAND_ALE)
  162. IO_ADDR_W |= CONFIG_SYS_NAND_ALE;
  163. if (ctrl & NAND_NCE) {
  164. writel(readl(&fsmc_regs_p->pc) |
  165. FSMC_ENABLE, &fsmc_regs_p->pc);
  166. } else {
  167. writel(readl(&fsmc_regs_p->pc) &
  168. ~FSMC_ENABLE, &fsmc_regs_p->pc);
  169. }
  170. this->IO_ADDR_W = (void *)IO_ADDR_W;
  171. }
  172. if (cmd != NAND_CMD_NONE)
  173. writeb(cmd, this->IO_ADDR_W);
  174. }
  175. static int fsmc_bch8_correct_data(struct mtd_info *mtd, u_char *dat,
  176. u_char *read_ecc, u_char *calc_ecc)
  177. {
  178. /* The calculated ecc is actually the correction index in data */
  179. u32 err_idx[8];
  180. u32 num_err, i;
  181. u32 ecc1, ecc2, ecc3, ecc4;
  182. num_err = (readl(&fsmc_regs_p->sts) >> 10) & 0xF;
  183. if (likely(num_err == 0))
  184. return 0;
  185. if (unlikely(num_err > 8)) {
  186. /*
  187. * This is a temporary erase check. A newly erased page read
  188. * would result in an ecc error because the oob data is also
  189. * erased to FF and the calculated ecc for an FF data is not
  190. * FF..FF.
  191. * This is a workaround to skip performing correction in case
  192. * data is FF..FF
  193. *
  194. * Logic:
  195. * For every page, each bit written as 0 is counted until these
  196. * number of bits are greater than 8 (the maximum correction
  197. * capability of FSMC for each 512 + 13 bytes)
  198. */
  199. int bits_ecc = count_written_bits(read_ecc, 13, 8);
  200. int bits_data = count_written_bits(dat, 512, 8);
  201. if ((bits_ecc + bits_data) <= 8) {
  202. if (bits_data)
  203. memset(dat, 0xff, 512);
  204. return bits_data + bits_ecc;
  205. }
  206. return -EBADMSG;
  207. }
  208. ecc1 = readl(&fsmc_regs_p->ecc1);
  209. ecc2 = readl(&fsmc_regs_p->ecc2);
  210. ecc3 = readl(&fsmc_regs_p->ecc3);
  211. ecc4 = readl(&fsmc_regs_p->sts);
  212. err_idx[0] = (ecc1 >> 0) & 0x1FFF;
  213. err_idx[1] = (ecc1 >> 13) & 0x1FFF;
  214. err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
  215. err_idx[3] = (ecc2 >> 7) & 0x1FFF;
  216. err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
  217. err_idx[5] = (ecc3 >> 1) & 0x1FFF;
  218. err_idx[6] = (ecc3 >> 14) & 0x1FFF;
  219. err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
  220. i = 0;
  221. while (i < num_err) {
  222. err_idx[i] ^= 3;
  223. if (err_idx[i] < 512 * 8)
  224. __change_bit(err_idx[i], dat);
  225. i++;
  226. }
  227. return num_err;
  228. }
  229. static int fsmc_read_hwecc(struct mtd_info *mtd,
  230. const u_char *data, u_char *ecc)
  231. {
  232. u_int ecc_tmp;
  233. int timeout = CONFIG_SYS_HZ;
  234. ulong start;
  235. switch (fsmc_version) {
  236. case FSMC_VER8:
  237. start = get_timer(0);
  238. while (get_timer(start) < timeout) {
  239. /*
  240. * Busy waiting for ecc computation
  241. * to finish for 512 bytes
  242. */
  243. if (readl(&fsmc_regs_p->sts) & FSMC_CODE_RDY)
  244. break;
  245. }
  246. ecc_tmp = readl(&fsmc_regs_p->ecc1);
  247. ecc[0] = (u_char) (ecc_tmp >> 0);
  248. ecc[1] = (u_char) (ecc_tmp >> 8);
  249. ecc[2] = (u_char) (ecc_tmp >> 16);
  250. ecc[3] = (u_char) (ecc_tmp >> 24);
  251. ecc_tmp = readl(&fsmc_regs_p->ecc2);
  252. ecc[4] = (u_char) (ecc_tmp >> 0);
  253. ecc[5] = (u_char) (ecc_tmp >> 8);
  254. ecc[6] = (u_char) (ecc_tmp >> 16);
  255. ecc[7] = (u_char) (ecc_tmp >> 24);
  256. ecc_tmp = readl(&fsmc_regs_p->ecc3);
  257. ecc[8] = (u_char) (ecc_tmp >> 0);
  258. ecc[9] = (u_char) (ecc_tmp >> 8);
  259. ecc[10] = (u_char) (ecc_tmp >> 16);
  260. ecc[11] = (u_char) (ecc_tmp >> 24);
  261. ecc_tmp = readl(&fsmc_regs_p->sts);
  262. ecc[12] = (u_char) (ecc_tmp >> 16);
  263. break;
  264. default:
  265. ecc_tmp = readl(&fsmc_regs_p->ecc1);
  266. ecc[0] = (u_char) (ecc_tmp >> 0);
  267. ecc[1] = (u_char) (ecc_tmp >> 8);
  268. ecc[2] = (u_char) (ecc_tmp >> 16);
  269. break;
  270. }
  271. return 0;
  272. }
  273. void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
  274. {
  275. writel(readl(&fsmc_regs_p->pc) & ~FSMC_ECCPLEN_256,
  276. &fsmc_regs_p->pc);
  277. writel(readl(&fsmc_regs_p->pc) & ~FSMC_ECCEN,
  278. &fsmc_regs_p->pc);
  279. writel(readl(&fsmc_regs_p->pc) | FSMC_ECCEN,
  280. &fsmc_regs_p->pc);
  281. }
  282. /*
  283. * fsmc_read_page_hwecc
  284. * @mtd: mtd info structure
  285. * @chip: nand chip info structure
  286. * @buf: buffer to store read data
  287. * @oob_required: caller expects OOB data read to chip->oob_poi
  288. * @page: page number to read
  289. *
  290. * This routine is needed for fsmc verison 8 as reading from NAND chip has to be
  291. * performed in a strict sequence as follows:
  292. * data(512 byte) -> ecc(13 byte)
  293. * After this read, fsmc hardware generates and reports error data bits(upto a
  294. * max of 8 bits)
  295. */
  296. static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
  297. uint8_t *buf, int oob_required, int page)
  298. {
  299. struct fsmc_eccplace *fsmc_eccpl;
  300. int i, j, s, stat, eccsize = chip->ecc.size;
  301. int eccbytes = chip->ecc.bytes;
  302. int eccsteps = chip->ecc.steps;
  303. uint8_t *p = buf;
  304. uint8_t *ecc_calc = chip->buffers->ecccalc;
  305. uint8_t *ecc_code = chip->buffers->ecccode;
  306. int off, len, group = 0;
  307. uint8_t oob[13] __attribute__ ((aligned (2)));
  308. /* Differentiate between small and large page ecc place definitions */
  309. if (mtd->writesize == 512)
  310. fsmc_eccpl = &fsmc_eccpl_sp;
  311. else
  312. fsmc_eccpl = &fsmc_eccpl_lp;
  313. for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
  314. chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
  315. chip->ecc.hwctl(mtd, NAND_ECC_READ);
  316. chip->read_buf(mtd, p, eccsize);
  317. for (j = 0; j < eccbytes;) {
  318. off = fsmc_eccpl->eccplace[group].offset;
  319. len = fsmc_eccpl->eccplace[group].length;
  320. group++;
  321. /*
  322. * length is intentionally kept a higher multiple of 2
  323. * to read at least 13 bytes even in case of 16 bit NAND
  324. * devices
  325. */
  326. if (chip->options & NAND_BUSWIDTH_16)
  327. len = roundup(len, 2);
  328. chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
  329. chip->read_buf(mtd, oob + j, len);
  330. j += len;
  331. }
  332. memcpy(&ecc_code[i], oob, 13);
  333. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  334. stat = chip->ecc.correct(mtd, p, &ecc_code[i],
  335. &ecc_calc[i]);
  336. if (stat < 0)
  337. mtd->ecc_stats.failed++;
  338. else
  339. mtd->ecc_stats.corrected += stat;
  340. }
  341. return 0;
  342. }
  343. int fsmc_nand_init(struct nand_chip *nand)
  344. {
  345. static int chip_nr;
  346. struct mtd_info *mtd;
  347. u32 peripid2 = readl(&fsmc_regs_p->peripid2);
  348. fsmc_version = (peripid2 >> FSMC_REVISION_SHFT) &
  349. FSMC_REVISION_MSK;
  350. writel(readl(&fsmc_regs_p->ctrl) | FSMC_WP, &fsmc_regs_p->ctrl);
  351. #if defined(CONFIG_SYS_FSMC_NAND_16BIT)
  352. writel(FSMC_DEVWID_16 | FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON,
  353. &fsmc_regs_p->pc);
  354. #elif defined(CONFIG_SYS_FSMC_NAND_8BIT)
  355. writel(FSMC_DEVWID_8 | FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON,
  356. &fsmc_regs_p->pc);
  357. #else
  358. #error Please define CONFIG_SYS_FSMC_NAND_16BIT or CONFIG_SYS_FSMC_NAND_8BIT
  359. #endif
  360. writel(readl(&fsmc_regs_p->pc) | FSMC_TCLR_1 | FSMC_TAR_1,
  361. &fsmc_regs_p->pc);
  362. writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
  363. &fsmc_regs_p->comm);
  364. writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
  365. &fsmc_regs_p->attrib);
  366. nand->options = 0;
  367. #if defined(CONFIG_SYS_FSMC_NAND_16BIT)
  368. nand->options |= NAND_BUSWIDTH_16;
  369. #endif
  370. nand->ecc.mode = NAND_ECC_HW;
  371. nand->ecc.size = 512;
  372. nand->ecc.calculate = fsmc_read_hwecc;
  373. nand->ecc.hwctl = fsmc_enable_hwecc;
  374. nand->cmd_ctrl = fsmc_nand_hwcontrol;
  375. nand->IO_ADDR_R = nand->IO_ADDR_W =
  376. (void __iomem *)CONFIG_SYS_NAND_BASE;
  377. nand->badblockbits = 7;
  378. mtd = nand_to_mtd(nand);
  379. switch (fsmc_version) {
  380. case FSMC_VER8:
  381. nand->ecc.bytes = 13;
  382. nand->ecc.strength = 8;
  383. nand->ecc.correct = fsmc_bch8_correct_data;
  384. nand->ecc.read_page = fsmc_read_page_hwecc;
  385. if (mtd->writesize == 512)
  386. nand->ecc.layout = &fsmc_ecc4_sp_layout;
  387. else {
  388. if (mtd->oobsize == 224)
  389. nand->ecc.layout = &fsmc_ecc4_224_layout;
  390. else
  391. nand->ecc.layout = &fsmc_ecc4_lp_layout;
  392. }
  393. break;
  394. default:
  395. nand->ecc.bytes = 3;
  396. nand->ecc.strength = 1;
  397. nand->ecc.layout = &fsmc_ecc1_layout;
  398. nand->ecc.correct = nand_correct_data;
  399. break;
  400. }
  401. /* Detect NAND chips */
  402. if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL))
  403. return -ENXIO;
  404. if (nand_scan_tail(mtd))
  405. return -ENXIO;
  406. if (nand_register(chip_nr++, mtd))
  407. return -ENXIO;
  408. return 0;
  409. }