Kconfig 50 KB

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  1. menu "ARM architecture"
  2. depends on ARM
  3. config SYS_ARCH
  4. default "arm"
  5. config ARM64
  6. bool
  7. select PHYS_64BIT
  8. select SYS_CACHE_SHIFT_6
  9. if ARM64
  10. config POSITION_INDEPENDENT
  11. bool "Generate position-independent pre-relocation code"
  12. help
  13. U-Boot expects to be linked to a specific hard-coded address, and to
  14. be loaded to and run from that address. This option lifts that
  15. restriction, thus allowing the code to be loaded to and executed from
  16. almost any 4K aligned address. This logic relies on the relocation
  17. information that is embedded in the binary to support U-Boot
  18. relocating itself to the top-of-RAM later during execution.
  19. config INIT_SP_RELATIVE
  20. bool "Specify the early stack pointer relative to the .bss section"
  21. default n if ARCH_QEMU
  22. default y if POSITION_INDEPENDENT
  23. help
  24. U-Boot typically uses a hard-coded value for the stack pointer
  25. before relocation. Enable this option to instead calculate the
  26. initial SP at run-time. This is useful to avoid hard-coding addresses
  27. into U-Boot, so that it can be loaded and executed at arbitrary
  28. addresses and thus avoid using arbitrary addresses at runtime.
  29. If this option is enabled, the early stack pointer is set to
  30. &_bss_start with a offset value added. The offset is specified by
  31. SYS_INIT_SP_BSS_OFFSET.
  32. config SYS_INIT_SP_BSS_OFFSET
  33. int "Early stack offset from the .bss base address"
  34. depends on INIT_SP_RELATIVE
  35. default 524288
  36. help
  37. This option's value is the offset added to &_bss_start in order to
  38. calculate the stack pointer. This offset should be large enough so
  39. that the early malloc region, global data (gd), and early stack usage
  40. do not overlap any appended DTB.
  41. config LINUX_KERNEL_IMAGE_HEADER
  42. bool
  43. help
  44. Place a Linux kernel image header at the start of the U-Boot binary.
  45. The format of the header is described in the Linux kernel source at
  46. Documentation/arm64/booting.txt. This feature is useful since the
  47. image header reports the amount of memory (BSS and similar) that
  48. U-Boot needs to use, but which isn't part of the binary.
  49. if LINUX_KERNEL_IMAGE_HEADER
  50. config LNX_KRNL_IMG_TEXT_OFFSET_BASE
  51. hex
  52. help
  53. The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the
  54. TEXT_OFFSET value written to the Linux kernel image header.
  55. endif
  56. endif
  57. config GIC_V3_ITS
  58. bool "ARM GICV3 ITS"
  59. select REGMAP
  60. select SYSCON
  61. select IRQ
  62. help
  63. ARM GICV3 Interrupt translation service (ITS).
  64. Basic support for programming locality specific peripheral
  65. interrupts (LPI) configuration tables and enable LPI tables.
  66. LPI configuration table can be used by u-boot or Linux.
  67. ARM GICV3 has limitation, once the LPI table is enabled, LPI
  68. configuration table can not be re-programmed, unless GICV3 reset.
  69. config STATIC_RELA
  70. bool
  71. default y if ARM64
  72. config DMA_ADDR_T_64BIT
  73. bool
  74. default y if ARM64
  75. config HAS_VBAR
  76. bool
  77. config HAS_THUMB2
  78. bool
  79. config GPIO_EXTRA_HEADER
  80. bool
  81. # Used for compatibility with asm files copied from the kernel
  82. config ARM_ASM_UNIFIED
  83. bool
  84. default y
  85. # Used for compatibility with asm files copied from the kernel
  86. config THUMB2_KERNEL
  87. bool
  88. config SYS_ICACHE_OFF
  89. bool "Do not enable icache"
  90. default n
  91. help
  92. Do not enable instruction cache in U-Boot.
  93. config SPL_SYS_ICACHE_OFF
  94. bool "Do not enable icache in SPL"
  95. depends on SPL
  96. default SYS_ICACHE_OFF
  97. help
  98. Do not enable instruction cache in SPL.
  99. config SYS_DCACHE_OFF
  100. bool "Do not enable dcache"
  101. default n
  102. help
  103. Do not enable data cache in U-Boot.
  104. config SPL_SYS_DCACHE_OFF
  105. bool "Do not enable dcache in SPL"
  106. depends on SPL
  107. default SYS_DCACHE_OFF
  108. help
  109. Do not enable data cache in SPL.
  110. config SYS_ARM_CACHE_CP15
  111. bool "CP15 based cache enabling support"
  112. help
  113. Select this if your processor suports enabling caches by using
  114. CP15 registers.
  115. config SYS_ARM_MMU
  116. bool "MMU-based Paged Memory Management Support"
  117. select SYS_ARM_CACHE_CP15
  118. help
  119. Select if you want MMU-based virtualised addressing space
  120. support via paged memory management.
  121. config SYS_ARM_MPU
  122. bool 'Use the ARM v7 PMSA Compliant MPU'
  123. help
  124. Some ARM systems without an MMU have instead a Memory Protection
  125. Unit (MPU) that defines the type and permissions for regions of
  126. memory.
  127. If your CPU has an MPU then you should choose 'y' here unless you
  128. know that you do not want to use the MPU.
  129. # If set, the workarounds for these ARM errata are applied early during U-Boot
  130. # startup. Note that in general these options force the workarounds to be
  131. # applied; no CPU-type/version detection exists, unlike the similar options in
  132. # the Linux kernel. Do not set these options unless they apply! Also note that
  133. # the following can be machine-specific errata. These do have ability to
  134. # provide rudimentary version and machine-specific checks, but expect no
  135. # product checks:
  136. # CONFIG_ARM_ERRATA_430973
  137. # CONFIG_ARM_ERRATA_454179
  138. # CONFIG_ARM_ERRATA_621766
  139. # CONFIG_ARM_ERRATA_798870
  140. # CONFIG_ARM_ERRATA_801819
  141. # CONFIG_ARM_CORTEX_A8_CVE_2017_5715
  142. # CONFIG_ARM_CORTEX_A15_CVE_2017_5715
  143. config ARM_ERRATA_430973
  144. bool
  145. config ARM_ERRATA_454179
  146. bool
  147. config ARM_ERRATA_621766
  148. bool
  149. config ARM_ERRATA_716044
  150. bool
  151. config ARM_ERRATA_725233
  152. bool
  153. config ARM_ERRATA_742230
  154. bool
  155. config ARM_ERRATA_743622
  156. bool
  157. config ARM_ERRATA_751472
  158. bool
  159. config ARM_ERRATA_761320
  160. bool
  161. config ARM_ERRATA_773022
  162. bool
  163. config ARM_ERRATA_774769
  164. bool
  165. config ARM_ERRATA_794072
  166. bool
  167. config ARM_ERRATA_798870
  168. bool
  169. config ARM_ERRATA_801819
  170. bool
  171. config ARM_ERRATA_826974
  172. bool
  173. config ARM_ERRATA_828024
  174. bool
  175. config ARM_ERRATA_829520
  176. bool
  177. config ARM_ERRATA_833069
  178. bool
  179. config ARM_ERRATA_833471
  180. bool
  181. config ARM_ERRATA_845369
  182. bool
  183. config ARM_ERRATA_852421
  184. bool
  185. config ARM_ERRATA_852423
  186. bool
  187. config ARM_ERRATA_855873
  188. bool
  189. config ARM_CORTEX_A8_CVE_2017_5715
  190. bool
  191. config ARM_CORTEX_A15_CVE_2017_5715
  192. bool
  193. config CPU_ARM720T
  194. bool
  195. select SYS_CACHE_SHIFT_5
  196. imply SYS_ARM_MMU
  197. config CPU_ARM920T
  198. bool
  199. select SYS_CACHE_SHIFT_5
  200. imply SYS_ARM_MMU
  201. config CPU_ARM926EJS
  202. bool
  203. select SYS_CACHE_SHIFT_5
  204. imply SYS_ARM_MMU
  205. config CPU_ARM946ES
  206. bool
  207. select SYS_CACHE_SHIFT_5
  208. imply SYS_ARM_MMU
  209. config CPU_ARM1136
  210. bool
  211. select SYS_CACHE_SHIFT_5
  212. imply SYS_ARM_MMU
  213. config CPU_ARM1176
  214. bool
  215. select HAS_VBAR
  216. select SYS_CACHE_SHIFT_5
  217. imply SYS_ARM_MMU
  218. config CPU_V7A
  219. bool
  220. select HAS_THUMB2
  221. select HAS_VBAR
  222. select SYS_CACHE_SHIFT_6
  223. imply SYS_ARM_MMU
  224. config CPU_V7M
  225. bool
  226. select HAS_THUMB2
  227. select SYS_ARM_MPU
  228. select SYS_CACHE_SHIFT_5
  229. select SYS_THUMB_BUILD
  230. select THUMB2_KERNEL
  231. config CPU_V7R
  232. bool
  233. select HAS_THUMB2
  234. select SYS_ARM_CACHE_CP15
  235. select SYS_ARM_MPU
  236. select SYS_CACHE_SHIFT_6
  237. config CPU_PXA
  238. bool
  239. select SYS_CACHE_SHIFT_5
  240. imply SYS_ARM_MMU
  241. config CPU_SA1100
  242. bool
  243. select SYS_CACHE_SHIFT_5
  244. imply SYS_ARM_MMU
  245. config SYS_CPU
  246. default "arm720t" if CPU_ARM720T
  247. default "arm920t" if CPU_ARM920T
  248. default "arm926ejs" if CPU_ARM926EJS
  249. default "arm946es" if CPU_ARM946ES
  250. default "arm1136" if CPU_ARM1136
  251. default "arm1176" if CPU_ARM1176
  252. default "armv7" if CPU_V7A
  253. default "armv7" if CPU_V7R
  254. default "armv7m" if CPU_V7M
  255. default "pxa" if CPU_PXA
  256. default "sa1100" if CPU_SA1100
  257. default "armv8" if ARM64
  258. config SYS_ARM_ARCH
  259. int
  260. default 4 if CPU_ARM720T
  261. default 4 if CPU_ARM920T
  262. default 5 if CPU_ARM926EJS
  263. default 5 if CPU_ARM946ES
  264. default 6 if CPU_ARM1136
  265. default 6 if CPU_ARM1176
  266. default 7 if CPU_V7A
  267. default 7 if CPU_V7M
  268. default 7 if CPU_V7R
  269. default 5 if CPU_PXA
  270. default 4 if CPU_SA1100
  271. default 8 if ARM64
  272. config SYS_CACHE_SHIFT_5
  273. bool
  274. config SYS_CACHE_SHIFT_6
  275. bool
  276. config SYS_CACHE_SHIFT_7
  277. bool
  278. config SYS_CACHELINE_SIZE
  279. int
  280. default 128 if SYS_CACHE_SHIFT_7
  281. default 64 if SYS_CACHE_SHIFT_6
  282. default 32 if SYS_CACHE_SHIFT_5
  283. choice
  284. prompt "Select the ARM data write cache policy"
  285. default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
  286. CPU_PXA || RZA1
  287. default SYS_ARM_CACHE_WRITEBACK
  288. config SYS_ARM_CACHE_WRITEBACK
  289. bool "Write-back (WB)"
  290. help
  291. A write updates the cache only and marks the cache line as dirty.
  292. External memory is updated only when the line is evicted or explicitly
  293. cleaned.
  294. config SYS_ARM_CACHE_WRITETHROUGH
  295. bool "Write-through (WT)"
  296. help
  297. A write updates both the cache and the external memory system.
  298. This does not mark the cache line as dirty.
  299. config SYS_ARM_CACHE_WRITEALLOC
  300. bool "Write allocation (WA)"
  301. help
  302. A cache line is allocated on a write miss. This means that executing a
  303. store instruction on the processor might cause a burst read to occur.
  304. There is a linefill to obtain the data for the cache line, before the
  305. write is performed.
  306. endchoice
  307. config ARCH_CPU_INIT
  308. bool "Enable ARCH_CPU_INIT"
  309. help
  310. Some architectures require a call to arch_cpu_init().
  311. Say Y here to enable it
  312. config SYS_ARCH_TIMER
  313. bool "ARM Generic Timer support"
  314. depends on CPU_V7A || ARM64
  315. default y if ARM64
  316. help
  317. The ARM Generic Timer (aka arch-timer) provides an architected
  318. interface to a timer source on an SoC.
  319. It is mandatory for ARMv8 implementation and widely available
  320. on ARMv7 systems.
  321. config ARM_SMCCC
  322. bool "Support for ARM SMC Calling Convention (SMCCC)"
  323. depends on CPU_V7A || ARM64
  324. select ARM_PSCI_FW
  325. help
  326. Say Y here if you want to enable ARM SMC Calling Convention.
  327. This should be enabled if U-Boot needs to communicate with system
  328. firmware (for example, PSCI) according to SMCCC.
  329. config SEMIHOSTING
  330. bool "support boot from semihosting"
  331. help
  332. In emulated environments, semihosting is a way for
  333. the hosted environment to call out to the emulator to
  334. retrieve files from the host machine.
  335. config SYS_THUMB_BUILD
  336. bool "Build U-Boot using the Thumb instruction set"
  337. depends on !ARM64
  338. help
  339. Use this flag to build U-Boot using the Thumb instruction set for
  340. ARM architectures. Thumb instruction set provides better code
  341. density. For ARM architectures that support Thumb2 this flag will
  342. result in Thumb2 code generated by GCC.
  343. config SPL_SYS_THUMB_BUILD
  344. bool "Build SPL using the Thumb instruction set"
  345. default y if SYS_THUMB_BUILD
  346. depends on !ARM64 && SPL
  347. help
  348. Use this flag to build SPL using the Thumb instruction set for
  349. ARM architectures. Thumb instruction set provides better code
  350. density. For ARM architectures that support Thumb2 this flag will
  351. result in Thumb2 code generated by GCC.
  352. config TPL_SYS_THUMB_BUILD
  353. bool "Build TPL using the Thumb instruction set"
  354. default y if SYS_THUMB_BUILD
  355. depends on TPL && !ARM64
  356. help
  357. Use this flag to build TPL using the Thumb instruction set for
  358. ARM architectures. Thumb instruction set provides better code
  359. density. For ARM architectures that support Thumb2 this flag will
  360. result in Thumb2 code generated by GCC.
  361. config SYS_L2CACHE_OFF
  362. bool "L2cache off"
  363. help
  364. If SoC does not support L2CACHE or one does not want to enable
  365. L2CACHE, choose this option.
  366. config ENABLE_ARM_SOC_BOOT0_HOOK
  367. bool "prepare BOOT0 header"
  368. help
  369. If the SoC's BOOT0 requires a header area filled with (magic)
  370. values, then choose this option, and create a file included as
  371. <asm/arch/boot0.h> which contains the required assembler code.
  372. config ARM_CORTEX_CPU_IS_UP
  373. bool
  374. default n
  375. config USE_ARCH_MEMCPY
  376. bool "Use an assembly optimized implementation of memcpy"
  377. default y
  378. depends on !ARM64
  379. help
  380. Enable the generation of an optimized version of memcpy.
  381. Such an implementation may be faster under some conditions
  382. but may increase the binary size.
  383. config SPL_USE_ARCH_MEMCPY
  384. bool "Use an assembly optimized implementation of memcpy for SPL"
  385. default y if USE_ARCH_MEMCPY
  386. depends on !ARM64 && SPL
  387. help
  388. Enable the generation of an optimized version of memcpy.
  389. Such an implementation may be faster under some conditions
  390. but may increase the binary size.
  391. config TPL_USE_ARCH_MEMCPY
  392. bool "Use an assembly optimized implementation of memcpy for TPL"
  393. default y if USE_ARCH_MEMCPY
  394. depends on !ARM64 && TPL
  395. help
  396. Enable the generation of an optimized version of memcpy.
  397. Such an implementation may be faster under some conditions
  398. but may increase the binary size.
  399. config USE_ARCH_MEMSET
  400. bool "Use an assembly optimized implementation of memset"
  401. default y
  402. depends on !ARM64
  403. help
  404. Enable the generation of an optimized version of memset.
  405. Such an implementation may be faster under some conditions
  406. but may increase the binary size.
  407. config SPL_USE_ARCH_MEMSET
  408. bool "Use an assembly optimized implementation of memset for SPL"
  409. default y if USE_ARCH_MEMSET
  410. depends on !ARM64 && SPL
  411. help
  412. Enable the generation of an optimized version of memset.
  413. Such an implementation may be faster under some conditions
  414. but may increase the binary size.
  415. config TPL_USE_ARCH_MEMSET
  416. bool "Use an assembly optimized implementation of memset for TPL"
  417. default y if USE_ARCH_MEMSET
  418. depends on !ARM64 && TPL
  419. help
  420. Enable the generation of an optimized version of memset.
  421. Such an implementation may be faster under some conditions
  422. but may increase the binary size.
  423. config ARM64_SUPPORT_AARCH32
  424. bool "ARM64 system support AArch32 execution state"
  425. depends on ARM64
  426. default y if !TARGET_THUNDERX_88XX
  427. help
  428. This ARM64 system supports AArch32 execution state.
  429. choice
  430. prompt "Target select"
  431. default TARGET_HIKEY
  432. config ARCH_AT91
  433. bool "Atmel AT91"
  434. select GPIO_EXTRA_HEADER
  435. select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
  436. select SPL_SEPARATE_BSS if SPL
  437. config TARGET_ASPENITE
  438. bool "Support aspenite"
  439. select CPU_ARM926EJS
  440. select GPIO_EXTRA_HEADER
  441. config ARCH_DAVINCI
  442. bool "TI DaVinci"
  443. select CPU_ARM926EJS
  444. select GPIO_EXTRA_HEADER
  445. select SPL_DM_SPI if SPL
  446. imply CMD_SAVES
  447. help
  448. Support for TI's DaVinci platform.
  449. config ARCH_KIRKWOOD
  450. bool "Marvell Kirkwood"
  451. select ARCH_MISC_INIT
  452. select BOARD_EARLY_INIT_F
  453. select CPU_ARM926EJS
  454. select GPIO_EXTRA_HEADER
  455. config ARCH_MVEBU
  456. bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
  457. select DM
  458. select DM_ETH
  459. select DM_SERIAL
  460. select DM_SPI
  461. select DM_SPI_FLASH
  462. select GPIO_EXTRA_HEADER
  463. select SPL_DM_SPI if SPL
  464. select SPL_DM_SPI_FLASH if SPL
  465. select OF_CONTROL
  466. select OF_SEPARATE
  467. select SPI
  468. imply CMD_DM
  469. config ARCH_ORION5X
  470. bool "Marvell Orion"
  471. select CPU_ARM926EJS
  472. select GPIO_EXTRA_HEADER
  473. config TARGET_STV0991
  474. bool "Support stv0991"
  475. select CPU_V7A
  476. select DM
  477. select DM_SERIAL
  478. select DM_SPI
  479. select DM_SPI_FLASH
  480. select GPIO_EXTRA_HEADER
  481. select PL01X_SERIAL
  482. select SPI
  483. select SPI_FLASH
  484. imply CMD_DM
  485. config TARGET_FLEA3
  486. bool "Support flea3"
  487. select CPU_ARM1136
  488. select GPIO_EXTRA_HEADER
  489. config ARCH_BCM283X
  490. bool "Broadcom BCM283X family"
  491. select DM
  492. select DM_GPIO
  493. select DM_SERIAL
  494. select GPIO_EXTRA_HEADER
  495. select OF_CONTROL
  496. select PL01X_SERIAL
  497. select SERIAL_SEARCH_ALL
  498. imply CMD_DM
  499. imply FAT_WRITE
  500. config ARCH_BCM63158
  501. bool "Broadcom BCM63158 family"
  502. select DM
  503. select OF_CONTROL
  504. imply CMD_DM
  505. config ARCH_BCM68360
  506. bool "Broadcom BCM68360 family"
  507. select DM
  508. select OF_CONTROL
  509. imply CMD_DM
  510. config ARCH_BCM6858
  511. bool "Broadcom BCM6858 family"
  512. select DM
  513. select OF_CONTROL
  514. imply CMD_DM
  515. config ARCH_BCMSTB
  516. bool "Broadcom BCM7XXX family"
  517. select CPU_V7A
  518. select DM
  519. select GPIO_EXTRA_HEADER
  520. select OF_CONTROL
  521. select OF_PRIOR_STAGE
  522. imply CMD_DM
  523. help
  524. This enables support for Broadcom ARM-based set-top box
  525. chipsets, including the 7445 family of chips.
  526. config TARGET_BCMCYGNUS
  527. bool "Support bcmcygnus"
  528. select CPU_V7A
  529. select GPIO_EXTRA_HEADER
  530. imply BCM_SF2_ETH
  531. imply BCM_SF2_ETH_GMAC
  532. imply CMD_HASH
  533. imply CRC32_VERIFY
  534. imply FAT_WRITE
  535. imply HASH_VERIFY
  536. imply NETDEVICES
  537. config TARGET_BCMNS2
  538. bool "Support Broadcom Northstar2"
  539. select ARM64
  540. select GPIO_EXTRA_HEADER
  541. help
  542. Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
  543. ARMv8 Cortex-A57 processors targeting a broad range of networking
  544. applications.
  545. config TARGET_BCMNS3
  546. bool "Support Broadcom NS3"
  547. select ARM64
  548. select BOARD_LATE_INIT
  549. help
  550. Support for Broadcom Northstar 3 SoCs. NS3 is a octo-core 64-bit
  551. ARMv8 Cortex-A72 processors targeting a broad range of networking
  552. applications.
  553. config ARCH_EXYNOS
  554. bool "Samsung EXYNOS"
  555. select DM
  556. select DM_GPIO
  557. select DM_I2C
  558. select DM_KEYBOARD
  559. select DM_SERIAL
  560. select DM_SPI
  561. select DM_SPI_FLASH
  562. select SPI
  563. select GPIO_EXTRA_HEADER
  564. imply SYS_THUMB_BUILD
  565. imply CMD_DM
  566. imply FAT_WRITE
  567. config ARCH_S5PC1XX
  568. bool "Samsung S5PC1XX"
  569. select CPU_V7A
  570. select DM
  571. select DM_GPIO
  572. select DM_I2C
  573. select DM_SERIAL
  574. select GPIO_EXTRA_HEADER
  575. imply CMD_DM
  576. config ARCH_HIGHBANK
  577. bool "Calxeda Highbank"
  578. select CPU_V7A
  579. select PL01X_SERIAL
  580. select DM
  581. select DM_SERIAL
  582. select OF_CONTROL
  583. select OF_BOARD
  584. select CLK
  585. select CLK_CCF
  586. select AHCI
  587. select DM_ETH
  588. select PHYS_64BIT
  589. config ARCH_INTEGRATOR
  590. bool "ARM Ltd. Integrator family"
  591. select DM
  592. select DM_SERIAL
  593. select GPIO_EXTRA_HEADER
  594. select PL01X_SERIAL
  595. imply CMD_DM
  596. config ARCH_IPQ40XX
  597. bool "Qualcomm IPQ40xx SoCs"
  598. select CPU_V7A
  599. select DM
  600. select DM_GPIO
  601. select DM_SERIAL
  602. select DM_RESET
  603. select GPIO_EXTRA_HEADER
  604. select MSM_SMEM
  605. select PINCTRL
  606. select CLK
  607. select SMEM
  608. select OF_CONTROL
  609. imply CMD_DM
  610. config ARCH_KEYSTONE
  611. bool "TI Keystone"
  612. select CMD_POWEROFF
  613. select CPU_V7A
  614. select GPIO_EXTRA_HEADER
  615. select SUPPORT_SPL
  616. select SYS_ARCH_TIMER
  617. select SYS_THUMB_BUILD
  618. imply CMD_MTDPARTS
  619. imply CMD_SAVES
  620. imply FIT
  621. config ARCH_K3
  622. bool "Texas Instruments' K3 Architecture"
  623. select SPL
  624. select SUPPORT_SPL
  625. select FIT
  626. config ARCH_OMAP2PLUS
  627. bool "TI OMAP2+"
  628. select CPU_V7A
  629. select GPIO_EXTRA_HEADER
  630. select SPL_BOARD_INIT if SPL
  631. select SPL_STACK_R if SPL
  632. select SUPPORT_SPL
  633. imply TI_SYSC if DM && OF_CONTROL
  634. imply FIT
  635. config ARCH_MESON
  636. bool "Amlogic Meson"
  637. select GPIO_EXTRA_HEADER
  638. imply DISTRO_DEFAULTS
  639. imply DM_RNG
  640. help
  641. Support for the Meson SoC family developed by Amlogic Inc.,
  642. targeted at media players and tablet computers. We currently
  643. support the S905 (GXBaby) 64-bit SoC.
  644. config ARCH_MEDIATEK
  645. bool "MediaTek SoCs"
  646. select DM
  647. select GPIO_EXTRA_HEADER
  648. select OF_CONTROL
  649. select SPL_DM if SPL
  650. select SPL_LIBCOMMON_SUPPORT if SPL
  651. select SPL_LIBGENERIC_SUPPORT if SPL
  652. select SPL_OF_CONTROL if SPL
  653. select SUPPORT_SPL
  654. help
  655. Support for the MediaTek SoCs family developed by MediaTek Inc.
  656. Please refer to doc/README.mediatek for more information.
  657. config ARCH_LPC32XX
  658. bool "NXP LPC32xx platform"
  659. select CPU_ARM926EJS
  660. select DM
  661. select DM_GPIO
  662. select DM_SERIAL
  663. select GPIO_EXTRA_HEADER
  664. select SPL_DM if SPL
  665. select SUPPORT_SPL
  666. imply CMD_DM
  667. config ARCH_IMX8
  668. bool "NXP i.MX8 platform"
  669. select ARM64
  670. select DM
  671. select GPIO_EXTRA_HEADER
  672. select OF_CONTROL
  673. select ENABLE_ARM_SOC_BOOT0_HOOK
  674. config ARCH_IMX8M
  675. bool "NXP i.MX8M platform"
  676. select ARM64
  677. select GPIO_EXTRA_HEADER
  678. select SYS_FSL_HAS_SEC if IMX_HAB
  679. select SYS_FSL_SEC_COMPAT_4
  680. select SYS_FSL_SEC_LE
  681. select DM
  682. select SUPPORT_SPL
  683. imply CMD_DM
  684. config ARCH_IMXRT
  685. bool "NXP i.MXRT platform"
  686. select CPU_V7M
  687. select DM
  688. select DM_SERIAL
  689. select GPIO_EXTRA_HEADER
  690. select SUPPORT_SPL
  691. imply CMD_DM
  692. config ARCH_MX23
  693. bool "NXP i.MX23 family"
  694. select CPU_ARM926EJS
  695. select GPIO_EXTRA_HEADER
  696. select PL011_SERIAL
  697. select SUPPORT_SPL
  698. config ARCH_MX25
  699. bool "NXP MX25"
  700. select CPU_ARM926EJS
  701. select GPIO_EXTRA_HEADER
  702. imply MXC_GPIO
  703. config ARCH_MX28
  704. bool "NXP i.MX28 family"
  705. select CPU_ARM926EJS
  706. select GPIO_EXTRA_HEADER
  707. select PL011_SERIAL
  708. select SUPPORT_SPL
  709. config ARCH_MX31
  710. bool "NXP i.MX31 family"
  711. select CPU_ARM1136
  712. select GPIO_EXTRA_HEADER
  713. config ARCH_MX7ULP
  714. bool "NXP MX7ULP"
  715. select CPU_V7A
  716. select GPIO_EXTRA_HEADER
  717. select SYS_FSL_HAS_SEC if IMX_HAB
  718. select SYS_FSL_SEC_COMPAT_4
  719. select SYS_FSL_SEC_LE
  720. select ROM_UNIFIED_SECTIONS
  721. imply MXC_GPIO
  722. imply SYS_THUMB_BUILD
  723. config ARCH_MX7
  724. bool "Freescale MX7"
  725. select ARCH_MISC_INIT
  726. select CPU_V7A
  727. select GPIO_EXTRA_HEADER
  728. select SYS_FSL_HAS_SEC if IMX_HAB
  729. select SYS_FSL_SEC_COMPAT_4
  730. select SYS_FSL_SEC_LE
  731. imply BOARD_EARLY_INIT_F
  732. imply MXC_GPIO
  733. imply SYS_THUMB_BUILD
  734. config ARCH_MX6
  735. bool "Freescale MX6"
  736. select CPU_V7A
  737. select GPIO_EXTRA_HEADER
  738. select SYS_FSL_HAS_SEC
  739. select SYS_FSL_SEC_COMPAT_4
  740. select SYS_FSL_SEC_LE
  741. imply MXC_GPIO
  742. imply SYS_THUMB_BUILD
  743. if ARCH_MX6
  744. config SPL_LDSCRIPT
  745. default "arch/arm/mach-omap2/u-boot-spl.lds"
  746. endif
  747. config ARCH_MX5
  748. bool "Freescale MX5"
  749. select BOARD_EARLY_INIT_F
  750. select CPU_V7A
  751. select GPIO_EXTRA_HEADER
  752. imply MXC_GPIO
  753. config ARCH_NEXELL
  754. bool "Nexell S5P4418/S5P6818 SoC"
  755. select ENABLE_ARM_SOC_BOOT0_HOOK
  756. select DM
  757. select GPIO_EXTRA_HEADER
  758. config ARCH_OWL
  759. bool "Actions Semi OWL SoCs"
  760. select DM
  761. select DM_ETH
  762. select DM_SERIAL
  763. select GPIO_EXTRA_HEADER
  764. select OWL_SERIAL
  765. select CLK
  766. select CLK_OWL
  767. select OF_CONTROL
  768. select SYS_RELOC_GD_ENV_ADDR
  769. imply CMD_DM
  770. config ARCH_QEMU
  771. bool "QEMU Virtual Platform"
  772. select DM
  773. select DM_SERIAL
  774. select OF_CONTROL
  775. select PL01X_SERIAL
  776. imply CMD_DM
  777. imply DM_RNG
  778. imply DM_RTC
  779. imply RTC_PL031
  780. config ARCH_RMOBILE
  781. bool "Renesas ARM SoCs"
  782. select DM
  783. select DM_SERIAL
  784. select GPIO_EXTRA_HEADER
  785. imply BOARD_EARLY_INIT_F
  786. imply CMD_DM
  787. imply FAT_WRITE
  788. imply SYS_THUMB_BUILD
  789. imply ARCH_MISC_INIT if DISPLAY_CPUINFO
  790. config ARCH_SNAPDRAGON
  791. bool "Qualcomm Snapdragon SoCs"
  792. select ARM64
  793. select DM
  794. select DM_GPIO
  795. select DM_SERIAL
  796. select GPIO_EXTRA_HEADER
  797. select MSM_SMEM
  798. select OF_CONTROL
  799. select OF_SEPARATE
  800. select SMEM
  801. select SPMI
  802. imply CMD_DM
  803. config ARCH_SOCFPGA
  804. bool "Altera SOCFPGA family"
  805. select ARCH_EARLY_INIT_R
  806. select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
  807. select ARM64 if TARGET_SOCFPGA_SOC64
  808. select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
  809. select DM
  810. select DM_SERIAL
  811. select GPIO_EXTRA_HEADER
  812. select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
  813. select OF_CONTROL
  814. select SPL_DM_RESET if DM_RESET
  815. select SPL_DM_SERIAL
  816. select SPL_LIBCOMMON_SUPPORT
  817. select SPL_LIBGENERIC_SUPPORT
  818. select SPL_NAND_SUPPORT if SPL_NAND_DENALI
  819. select SPL_OF_CONTROL
  820. select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
  821. select SPL_SERIAL_SUPPORT
  822. select SPL_SYSRESET
  823. select SPL_WATCHDOG_SUPPORT
  824. select SUPPORT_SPL
  825. select SYS_NS16550
  826. select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
  827. select SYSRESET
  828. select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
  829. select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64
  830. imply CMD_DM
  831. imply CMD_MTDPARTS
  832. imply CRC32_VERIFY
  833. imply DM_SPI
  834. imply DM_SPI_FLASH
  835. imply FAT_WRITE
  836. imply SPL
  837. imply SPL_DM
  838. imply SPL_DM_SPI
  839. imply SPL_DM_SPI_FLASH
  840. imply SPL_LIBDISK_SUPPORT
  841. imply SPL_MMC_SUPPORT
  842. imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
  843. imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
  844. imply SPL_SPI_FLASH_SUPPORT
  845. imply SPL_SPI_SUPPORT
  846. imply L2X0_CACHE
  847. config ARCH_SUNXI
  848. bool "Support sunxi (Allwinner) SoCs"
  849. select BINMAN
  850. select CMD_GPIO
  851. select CMD_MMC if MMC
  852. select CMD_USB if DISTRO_DEFAULTS
  853. select CLK
  854. select DM
  855. select DM_ETH
  856. select DM_GPIO
  857. select DM_KEYBOARD
  858. select DM_MMC if MMC
  859. select DM_SCSI if SCSI
  860. select DM_SERIAL
  861. select DM_USB if DISTRO_DEFAULTS
  862. select GPIO_EXTRA_HEADER
  863. select OF_BOARD_SETUP
  864. select OF_CONTROL
  865. select OF_SEPARATE
  866. select SPECIFY_CONSOLE_INDEX
  867. select SPL_STACK_R if SPL
  868. select SPL_SYS_MALLOC_SIMPLE if SPL
  869. select SPL_SYS_THUMB_BUILD if !ARM64
  870. select SUNXI_GPIO
  871. select SYS_NS16550
  872. select SYS_THUMB_BUILD if !ARM64
  873. select USB if DISTRO_DEFAULTS
  874. select USB_KEYBOARD if DISTRO_DEFAULTS
  875. select USB_STORAGE if DISTRO_DEFAULTS
  876. select SPL_USE_TINY_PRINTF
  877. select USE_PREBOOT
  878. select SYS_RELOC_GD_ENV_ADDR
  879. imply BOARD_LATE_INIT
  880. imply CMD_DM
  881. imply CMD_GPT
  882. imply CMD_UBI if MTD_RAW_NAND
  883. imply DISTRO_DEFAULTS
  884. imply FAT_WRITE
  885. imply FIT
  886. imply OF_LIBFDT_OVERLAY
  887. imply PRE_CONSOLE_BUFFER
  888. imply SPL_GPIO_SUPPORT
  889. imply SPL_LIBCOMMON_SUPPORT
  890. imply SPL_LIBGENERIC_SUPPORT
  891. imply SPL_MMC_SUPPORT if MMC
  892. imply SPL_POWER_SUPPORT
  893. imply SPL_SERIAL_SUPPORT
  894. imply USB_GADGET
  895. config ARCH_U8500
  896. bool "ST-Ericsson U8500 Series"
  897. select CPU_V7A
  898. select DM
  899. select DM_GPIO
  900. select DM_MMC if MMC
  901. select DM_SERIAL
  902. select DM_USB if USB
  903. select OF_CONTROL
  904. select SYSRESET
  905. select TIMER
  906. imply ARM_PL180_MMCI
  907. imply DM_RTC
  908. imply NOMADIK_MTU_TIMER
  909. imply PL01X_SERIAL
  910. imply RTC_PL031
  911. imply SYSRESET_SYSCON
  912. config ARCH_VERSAL
  913. bool "Support Xilinx Versal Platform"
  914. select ARM64
  915. select CLK
  916. select DM
  917. select DM_ETH if NET
  918. select DM_MMC if MMC
  919. select DM_SERIAL
  920. select GPIO_EXTRA_HEADER
  921. select OF_CONTROL
  922. imply BOARD_LATE_INIT
  923. imply ENV_VARS_UBOOT_RUNTIME_CONFIG
  924. config ARCH_VF610
  925. bool "Freescale Vybrid"
  926. select CPU_V7A
  927. select GPIO_EXTRA_HEADER
  928. select SYS_FSL_ERRATUM_ESDHC111
  929. imply CMD_MTDPARTS
  930. imply MTD_RAW_NAND
  931. config ARCH_ZYNQ
  932. bool "Xilinx Zynq based platform"
  933. select CLK
  934. select CLK_ZYNQ
  935. select CPU_V7A
  936. select DM
  937. select DM_ETH if NET
  938. select DM_MMC if MMC
  939. select DM_SERIAL
  940. select DM_SPI
  941. select DM_SPI_FLASH
  942. select DM_USB if USB
  943. select GPIO_EXTRA_HEADER
  944. select OF_CONTROL
  945. select SPI
  946. select SPL_BOARD_INIT if SPL
  947. select SPL_CLK if SPL
  948. select SPL_DM if SPL
  949. select SPL_DM_SPI if SPL
  950. select SPL_DM_SPI_FLASH if SPL
  951. select SPL_OF_CONTROL if SPL
  952. select SPL_SEPARATE_BSS if SPL
  953. select SUPPORT_SPL
  954. imply ARCH_EARLY_INIT_R
  955. imply BOARD_LATE_INIT
  956. imply CMD_CLK
  957. imply CMD_DM
  958. imply CMD_SPL
  959. imply ENV_VARS_UBOOT_RUNTIME_CONFIG
  960. imply FAT_WRITE
  961. config ARCH_ZYNQMP_R5
  962. bool "Xilinx ZynqMP R5 based platform"
  963. select CLK
  964. select CPU_V7R
  965. select DM
  966. select DM_ETH if NET
  967. select DM_MMC if MMC
  968. select DM_SERIAL
  969. select GPIO_EXTRA_HEADER
  970. select OF_CONTROL
  971. imply CMD_DM
  972. imply DM_USB_GADGET
  973. config ARCH_ZYNQMP
  974. bool "Xilinx ZynqMP based platform"
  975. select ARM64
  976. select CLK
  977. select DM
  978. select DM_ETH if NET
  979. select DM_MAILBOX
  980. select DM_MMC if MMC
  981. select DM_SERIAL
  982. select DM_SPI if SPI
  983. select DM_SPI_FLASH if DM_SPI
  984. select DM_USB if USB
  985. select FIRMWARE
  986. select GPIO_EXTRA_HEADER
  987. select OF_CONTROL
  988. select SPL_BOARD_INIT if SPL
  989. select SPL_CLK if SPL
  990. select SPL_DM if SPL
  991. select SPL_DM_SPI if SPI && SPL_DM
  992. select SPL_DM_SPI_FLASH if SPL_DM_SPI
  993. select SPL_DM_MAILBOX if SPL
  994. select SPL_FIRMWARE if SPL
  995. select SPL_SEPARATE_BSS if SPL
  996. select SUPPORT_SPL
  997. select ZYNQMP_IPI
  998. imply BOARD_LATE_INIT
  999. imply CMD_DM
  1000. imply ENV_VARS_UBOOT_RUNTIME_CONFIG
  1001. imply FAT_WRITE
  1002. imply MP
  1003. imply DM_USB_GADGET
  1004. config ARCH_TEGRA
  1005. bool "NVIDIA Tegra"
  1006. select GPIO_EXTRA_HEADER
  1007. imply DISTRO_DEFAULTS
  1008. imply FAT_WRITE
  1009. config TARGET_VEXPRESS64_AEMV8A
  1010. bool "Support vexpress_aemv8a"
  1011. select ARM64
  1012. select GPIO_EXTRA_HEADER
  1013. select PL01X_SERIAL
  1014. config TARGET_VEXPRESS64_BASE_FVP
  1015. bool "Support Versatile Express ARMv8a FVP BASE model"
  1016. select ARM64
  1017. select GPIO_EXTRA_HEADER
  1018. select PL01X_SERIAL
  1019. select SEMIHOSTING
  1020. config TARGET_VEXPRESS64_JUNO
  1021. bool "Support Versatile Express Juno Development Platform"
  1022. select ARM64
  1023. select GPIO_EXTRA_HEADER
  1024. select PL01X_SERIAL
  1025. select DM
  1026. select OF_CONTROL
  1027. select OF_BOARD
  1028. select CLK
  1029. select DM_SERIAL
  1030. select ARM_PSCI_FW
  1031. select PSCI_RESET
  1032. select DM_ETH
  1033. select BLK
  1034. select USB
  1035. select DM_USB
  1036. config TARGET_TOTAL_COMPUTE
  1037. bool "Support Total Compute Platform"
  1038. select ARM64
  1039. select PL01X_SERIAL
  1040. select DM
  1041. select DM_SERIAL
  1042. select DM_MMC
  1043. select DM_GPIO
  1044. config TARGET_LS2080A_EMU
  1045. bool "Support ls2080a_emu"
  1046. select ARCH_LS2080A
  1047. select ARM64
  1048. select ARMV8_MULTIENTRY
  1049. select FSL_DDR_SYNC_REFRESH
  1050. select GPIO_EXTRA_HEADER
  1051. help
  1052. Support for Freescale LS2080A_EMU platform.
  1053. The LS2080A Development System (EMULATOR) is a pre-silicon
  1054. development platform that supports the QorIQ LS2080A
  1055. Layerscape Architecture processor.
  1056. config TARGET_LS1088AQDS
  1057. bool "Support ls1088aqds"
  1058. select ARCH_LS1088A
  1059. select ARM64
  1060. select ARMV8_MULTIENTRY
  1061. select ARCH_SUPPORT_TFABOOT
  1062. select BOARD_LATE_INIT
  1063. select GPIO_EXTRA_HEADER
  1064. select SUPPORT_SPL
  1065. select FSL_DDR_INTERACTIVE if !SD_BOOT
  1066. help
  1067. Support for NXP LS1088AQDS platform.
  1068. The LS1088A Development System (QDS) is a high-performance
  1069. development platform that supports the QorIQ LS1088A
  1070. Layerscape Architecture processor.
  1071. config TARGET_LS2080AQDS
  1072. bool "Support ls2080aqds"
  1073. select ARCH_LS2080A
  1074. select ARM64
  1075. select ARMV8_MULTIENTRY
  1076. select ARCH_SUPPORT_TFABOOT
  1077. select BOARD_LATE_INIT
  1078. select GPIO_EXTRA_HEADER
  1079. select SUPPORT_SPL
  1080. imply SCSI
  1081. imply SCSI_AHCI
  1082. select FSL_DDR_BIST
  1083. select FSL_DDR_INTERACTIVE if !SPL
  1084. help
  1085. Support for Freescale LS2080AQDS platform.
  1086. The LS2080A Development System (QDS) is a high-performance
  1087. development platform that supports the QorIQ LS2080A
  1088. Layerscape Architecture processor.
  1089. config TARGET_LS2080ARDB
  1090. bool "Support ls2080ardb"
  1091. select ARCH_LS2080A
  1092. select ARM64
  1093. select ARMV8_MULTIENTRY
  1094. select ARCH_SUPPORT_TFABOOT
  1095. select BOARD_LATE_INIT
  1096. select SUPPORT_SPL
  1097. select FSL_DDR_BIST
  1098. select FSL_DDR_INTERACTIVE if !SPL
  1099. select GPIO_EXTRA_HEADER
  1100. imply SCSI
  1101. imply SCSI_AHCI
  1102. help
  1103. Support for Freescale LS2080ARDB platform.
  1104. The LS2080A Reference design board (RDB) is a high-performance
  1105. development platform that supports the QorIQ LS2080A
  1106. Layerscape Architecture processor.
  1107. config TARGET_LS2081ARDB
  1108. bool "Support ls2081ardb"
  1109. select ARCH_LS2080A
  1110. select ARM64
  1111. select ARMV8_MULTIENTRY
  1112. select BOARD_LATE_INIT
  1113. select GPIO_EXTRA_HEADER
  1114. select SUPPORT_SPL
  1115. help
  1116. Support for Freescale LS2081ARDB platform.
  1117. The LS2081A Reference design board (RDB) is a high-performance
  1118. development platform that supports the QorIQ LS2081A/LS2041A
  1119. Layerscape Architecture processor.
  1120. config TARGET_LX2160ARDB
  1121. bool "Support lx2160ardb"
  1122. select ARCH_LX2160A
  1123. select ARM64
  1124. select ARMV8_MULTIENTRY
  1125. select ARCH_SUPPORT_TFABOOT
  1126. select BOARD_LATE_INIT
  1127. select GPIO_EXTRA_HEADER
  1128. help
  1129. Support for NXP LX2160ARDB platform.
  1130. The lx2160ardb (LX2160A Reference design board (RDB)
  1131. is a high-performance development platform that supports the
  1132. QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
  1133. config TARGET_LX2160AQDS
  1134. bool "Support lx2160aqds"
  1135. select ARCH_LX2160A
  1136. select ARM64
  1137. select ARMV8_MULTIENTRY
  1138. select ARCH_SUPPORT_TFABOOT
  1139. select BOARD_LATE_INIT
  1140. select GPIO_EXTRA_HEADER
  1141. help
  1142. Support for NXP LX2160AQDS platform.
  1143. The lx2160aqds (LX2160A QorIQ Development System (QDS)
  1144. is a high-performance development platform that supports the
  1145. QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
  1146. config TARGET_LX2162AQDS
  1147. bool "Support lx2162aqds"
  1148. select ARCH_LX2162A
  1149. select ARCH_MISC_INIT
  1150. select ARM64
  1151. select ARMV8_MULTIENTRY
  1152. select ARCH_SUPPORT_TFABOOT
  1153. select BOARD_LATE_INIT
  1154. select GPIO_EXTRA_HEADER
  1155. help
  1156. Support for NXP LX2162AQDS platform.
  1157. The lx2162aqds support is based on LX2160A Layerscape Architecture processor.
  1158. config TARGET_HIKEY
  1159. bool "Support HiKey 96boards Consumer Edition Platform"
  1160. select ARM64
  1161. select DM
  1162. select DM_GPIO
  1163. select DM_SERIAL
  1164. select GPIO_EXTRA_HEADER
  1165. select OF_CONTROL
  1166. select PL01X_SERIAL
  1167. select SPECIFY_CONSOLE_INDEX
  1168. imply CMD_DM
  1169. help
  1170. Support for HiKey 96boards platform. It features a HI6220
  1171. SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
  1172. config TARGET_HIKEY960
  1173. bool "Support HiKey960 96boards Consumer Edition Platform"
  1174. select ARM64
  1175. select DM
  1176. select DM_SERIAL
  1177. select GPIO_EXTRA_HEADER
  1178. select OF_CONTROL
  1179. select PL01X_SERIAL
  1180. imply CMD_DM
  1181. help
  1182. Support for HiKey960 96boards platform. It features a HI3660
  1183. SoC, with 4xA73 CPU, 4xA53 CPU, MALI-G71 GPU, and 3GB RAM.
  1184. config TARGET_POPLAR
  1185. bool "Support Poplar 96boards Enterprise Edition Platform"
  1186. select ARM64
  1187. select DM
  1188. select DM_SERIAL
  1189. select DM_USB
  1190. select GPIO_EXTRA_HEADER
  1191. select OF_CONTROL
  1192. select PL01X_SERIAL
  1193. imply CMD_DM
  1194. help
  1195. Support for Poplar 96boards EE platform. It features a HI3798cv200
  1196. SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
  1197. making it capable of running any commercial set-top solution based on
  1198. Linux or Android.
  1199. config TARGET_LS1012AQDS
  1200. bool "Support ls1012aqds"
  1201. select ARCH_LS1012A
  1202. select ARM64
  1203. select ARCH_SUPPORT_TFABOOT
  1204. select BOARD_LATE_INIT
  1205. select GPIO_EXTRA_HEADER
  1206. help
  1207. Support for Freescale LS1012AQDS platform.
  1208. The LS1012A Development System (QDS) is a high-performance
  1209. development platform that supports the QorIQ LS1012A
  1210. Layerscape Architecture processor.
  1211. config TARGET_LS1012ARDB
  1212. bool "Support ls1012ardb"
  1213. select ARCH_LS1012A
  1214. select ARM64
  1215. select ARCH_SUPPORT_TFABOOT
  1216. select BOARD_LATE_INIT
  1217. select GPIO_EXTRA_HEADER
  1218. imply SCSI
  1219. imply SCSI_AHCI
  1220. help
  1221. Support for Freescale LS1012ARDB platform.
  1222. The LS1012A Reference design board (RDB) is a high-performance
  1223. development platform that supports the QorIQ LS1012A
  1224. Layerscape Architecture processor.
  1225. config TARGET_LS1012A2G5RDB
  1226. bool "Support ls1012a2g5rdb"
  1227. select ARCH_LS1012A
  1228. select ARM64
  1229. select ARCH_SUPPORT_TFABOOT
  1230. select BOARD_LATE_INIT
  1231. select GPIO_EXTRA_HEADER
  1232. imply SCSI
  1233. help
  1234. Support for Freescale LS1012A2G5RDB platform.
  1235. The LS1012A 2G5 Reference design board (RDB) is a high-performance
  1236. development platform that supports the QorIQ LS1012A
  1237. Layerscape Architecture processor.
  1238. config TARGET_LS1012AFRWY
  1239. bool "Support ls1012afrwy"
  1240. select ARCH_LS1012A
  1241. select ARM64
  1242. select ARCH_SUPPORT_TFABOOT
  1243. select BOARD_LATE_INIT
  1244. select GPIO_EXTRA_HEADER
  1245. imply SCSI
  1246. imply SCSI_AHCI
  1247. help
  1248. Support for Freescale LS1012AFRWY platform.
  1249. The LS1012A FRWY board (FRWY) is a high-performance
  1250. development platform that supports the QorIQ LS1012A
  1251. Layerscape Architecture processor.
  1252. config TARGET_LS1012AFRDM
  1253. bool "Support ls1012afrdm"
  1254. select ARCH_LS1012A
  1255. select ARM64
  1256. select ARCH_SUPPORT_TFABOOT
  1257. select GPIO_EXTRA_HEADER
  1258. help
  1259. Support for Freescale LS1012AFRDM platform.
  1260. The LS1012A Freedom board (FRDM) is a high-performance
  1261. development platform that supports the QorIQ LS1012A
  1262. Layerscape Architecture processor.
  1263. config TARGET_LS1028AQDS
  1264. bool "Support ls1028aqds"
  1265. select ARCH_LS1028A
  1266. select ARM64
  1267. select ARMV8_MULTIENTRY
  1268. select ARCH_SUPPORT_TFABOOT
  1269. select BOARD_LATE_INIT
  1270. select GPIO_EXTRA_HEADER
  1271. help
  1272. Support for Freescale LS1028AQDS platform
  1273. The LS1028A Development System (QDS) is a high-performance
  1274. development platform that supports the QorIQ LS1028A
  1275. Layerscape Architecture processor.
  1276. config TARGET_LS1028ARDB
  1277. bool "Support ls1028ardb"
  1278. select ARCH_LS1028A
  1279. select ARM64
  1280. select ARMV8_MULTIENTRY
  1281. select ARCH_SUPPORT_TFABOOT
  1282. select BOARD_LATE_INIT
  1283. select GPIO_EXTRA_HEADER
  1284. help
  1285. Support for Freescale LS1028ARDB platform
  1286. The LS1028A Development System (RDB) is a high-performance
  1287. development platform that supports the QorIQ LS1028A
  1288. Layerscape Architecture processor.
  1289. config TARGET_LS1088ARDB
  1290. bool "Support ls1088ardb"
  1291. select ARCH_LS1088A
  1292. select ARM64
  1293. select ARMV8_MULTIENTRY
  1294. select ARCH_SUPPORT_TFABOOT
  1295. select BOARD_LATE_INIT
  1296. select SUPPORT_SPL
  1297. select FSL_DDR_INTERACTIVE if !SD_BOOT
  1298. select GPIO_EXTRA_HEADER
  1299. help
  1300. Support for NXP LS1088ARDB platform.
  1301. The LS1088A Reference design board (RDB) is a high-performance
  1302. development platform that supports the QorIQ LS1088A
  1303. Layerscape Architecture processor.
  1304. config TARGET_LS1021AQDS
  1305. bool "Support ls1021aqds"
  1306. select ARCH_LS1021A
  1307. select ARCH_SUPPORT_PSCI
  1308. select BOARD_EARLY_INIT_F
  1309. select BOARD_LATE_INIT
  1310. select CPU_V7A
  1311. select CPU_V7_HAS_NONSEC
  1312. select CPU_V7_HAS_VIRT
  1313. select LS1_DEEP_SLEEP
  1314. select SUPPORT_SPL
  1315. select SYS_FSL_DDR
  1316. select FSL_DDR_INTERACTIVE
  1317. select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
  1318. select GPIO_EXTRA_HEADER
  1319. select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI
  1320. imply SCSI
  1321. config TARGET_LS1021ATWR
  1322. bool "Support ls1021atwr"
  1323. select ARCH_LS1021A
  1324. select ARCH_SUPPORT_PSCI
  1325. select BOARD_EARLY_INIT_F
  1326. select BOARD_LATE_INIT
  1327. select CPU_V7A
  1328. select CPU_V7_HAS_NONSEC
  1329. select CPU_V7_HAS_VIRT
  1330. select LS1_DEEP_SLEEP
  1331. select SUPPORT_SPL
  1332. select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
  1333. select GPIO_EXTRA_HEADER
  1334. imply SCSI
  1335. config TARGET_PG_WCOM_SELI8
  1336. bool "Support Hitachi-Powergrids SELI8 service unit card"
  1337. select ARCH_LS1021A
  1338. select ARCH_SUPPORT_PSCI
  1339. select BOARD_EARLY_INIT_F
  1340. select BOARD_LATE_INIT
  1341. select CPU_V7A
  1342. select CPU_V7_HAS_NONSEC
  1343. select CPU_V7_HAS_VIRT
  1344. select SYS_FSL_DDR
  1345. select FSL_DDR_INTERACTIVE
  1346. select GPIO_EXTRA_HEADER
  1347. select VENDOR_KM
  1348. imply SCSI
  1349. help
  1350. Support for Hitachi-Powergrids SELI8 service unit card.
  1351. SELI8 is a QorIQ LS1021a based service unit card used
  1352. in XMC20 and FOX615 product families.
  1353. config TARGET_PG_WCOM_EXPU1
  1354. bool "Support Hitachi-Powergrids EXPU1 service unit card"
  1355. select ARCH_LS1021A
  1356. select ARCH_SUPPORT_PSCI
  1357. select BOARD_EARLY_INIT_F
  1358. select BOARD_LATE_INIT
  1359. select CPU_V7A
  1360. select CPU_V7_HAS_NONSEC
  1361. select CPU_V7_HAS_VIRT
  1362. select SYS_FSL_DDR
  1363. select FSL_DDR_INTERACTIVE
  1364. select VENDOR_KM
  1365. imply SCSI
  1366. help
  1367. Support for Hitachi-Powergrids EXPU1 service unit card.
  1368. EXPU1 is a QorIQ LS1021a based service unit card used
  1369. in XMC20 and FOX615 product families.
  1370. config TARGET_LS1021ATSN
  1371. bool "Support ls1021atsn"
  1372. select ARCH_LS1021A
  1373. select ARCH_SUPPORT_PSCI
  1374. select BOARD_EARLY_INIT_F
  1375. select BOARD_LATE_INIT
  1376. select CPU_V7A
  1377. select CPU_V7_HAS_NONSEC
  1378. select CPU_V7_HAS_VIRT
  1379. select LS1_DEEP_SLEEP
  1380. select SUPPORT_SPL
  1381. select GPIO_EXTRA_HEADER
  1382. imply SCSI
  1383. config TARGET_LS1021AIOT
  1384. bool "Support ls1021aiot"
  1385. select ARCH_LS1021A
  1386. select ARCH_SUPPORT_PSCI
  1387. select BOARD_LATE_INIT
  1388. select CPU_V7A
  1389. select CPU_V7_HAS_NONSEC
  1390. select CPU_V7_HAS_VIRT
  1391. select SUPPORT_SPL
  1392. select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
  1393. select GPIO_EXTRA_HEADER
  1394. imply SCSI
  1395. help
  1396. Support for Freescale LS1021AIOT platform.
  1397. The LS1021A Freescale board (IOT) is a high-performance
  1398. development platform that supports the QorIQ LS1021A
  1399. Layerscape Architecture processor.
  1400. config TARGET_LS1043AQDS
  1401. bool "Support ls1043aqds"
  1402. select ARCH_LS1043A
  1403. select ARM64
  1404. select ARMV8_MULTIENTRY
  1405. select ARCH_SUPPORT_TFABOOT
  1406. select BOARD_EARLY_INIT_F
  1407. select BOARD_LATE_INIT
  1408. select SUPPORT_SPL
  1409. select FSL_DDR_INTERACTIVE if !SPL
  1410. select FSL_DSPI if !SPL_NO_DSPI
  1411. select DM_SPI_FLASH if FSL_DSPI
  1412. select GPIO_EXTRA_HEADER
  1413. imply SCSI
  1414. imply SCSI_AHCI
  1415. help
  1416. Support for Freescale LS1043AQDS platform.
  1417. config TARGET_LS1043ARDB
  1418. bool "Support ls1043ardb"
  1419. select ARCH_LS1043A
  1420. select ARM64
  1421. select ARMV8_MULTIENTRY
  1422. select ARCH_SUPPORT_TFABOOT
  1423. select BOARD_EARLY_INIT_F
  1424. select BOARD_LATE_INIT
  1425. select SUPPORT_SPL
  1426. select FSL_DSPI if !SPL_NO_DSPI
  1427. select DM_SPI_FLASH if FSL_DSPI
  1428. select GPIO_EXTRA_HEADER
  1429. help
  1430. Support for Freescale LS1043ARDB platform.
  1431. config TARGET_LS1046AQDS
  1432. bool "Support ls1046aqds"
  1433. select ARCH_LS1046A
  1434. select ARM64
  1435. select ARMV8_MULTIENTRY
  1436. select ARCH_SUPPORT_TFABOOT
  1437. select BOARD_EARLY_INIT_F
  1438. select BOARD_LATE_INIT
  1439. select DM_SPI_FLASH if DM_SPI
  1440. select SUPPORT_SPL
  1441. select FSL_DDR_BIST if !SPL
  1442. select FSL_DDR_INTERACTIVE if !SPL
  1443. select FSL_DDR_INTERACTIVE if !SPL
  1444. select GPIO_EXTRA_HEADER
  1445. imply SCSI
  1446. help
  1447. Support for Freescale LS1046AQDS platform.
  1448. The LS1046A Development System (QDS) is a high-performance
  1449. development platform that supports the QorIQ LS1046A
  1450. Layerscape Architecture processor.
  1451. config TARGET_LS1046ARDB
  1452. bool "Support ls1046ardb"
  1453. select ARCH_LS1046A
  1454. select ARM64
  1455. select ARMV8_MULTIENTRY
  1456. select ARCH_SUPPORT_TFABOOT
  1457. select BOARD_EARLY_INIT_F
  1458. select BOARD_LATE_INIT
  1459. select DM_SPI_FLASH if DM_SPI
  1460. select POWER_MC34VR500
  1461. select SUPPORT_SPL
  1462. select FSL_DDR_BIST
  1463. select FSL_DDR_INTERACTIVE if !SPL
  1464. select GPIO_EXTRA_HEADER
  1465. imply SCSI
  1466. help
  1467. Support for Freescale LS1046ARDB platform.
  1468. The LS1046A Reference Design Board (RDB) is a high-performance
  1469. development platform that supports the QorIQ LS1046A
  1470. Layerscape Architecture processor.
  1471. config TARGET_LS1046AFRWY
  1472. bool "Support ls1046afrwy"
  1473. select ARCH_LS1046A
  1474. select ARM64
  1475. select ARMV8_MULTIENTRY
  1476. select ARCH_SUPPORT_TFABOOT
  1477. select BOARD_EARLY_INIT_F
  1478. select BOARD_LATE_INIT
  1479. select DM_SPI_FLASH if DM_SPI
  1480. select GPIO_EXTRA_HEADER
  1481. imply SCSI
  1482. help
  1483. Support for Freescale LS1046AFRWY platform.
  1484. The LS1046A Freeway Board (FRWY) is a high-performance
  1485. development platform that supports the QorIQ LS1046A
  1486. Layerscape Architecture processor.
  1487. config TARGET_SL28
  1488. bool "Support sl28"
  1489. select ARCH_LS1028A
  1490. select ARM64
  1491. select ARMV8_MULTIENTRY
  1492. select SUPPORT_SPL
  1493. select BINMAN
  1494. select DM
  1495. select DM_GPIO
  1496. select DM_I2C
  1497. select DM_MMC
  1498. select DM_SPI_FLASH
  1499. select DM_ETH
  1500. select DM_MDIO
  1501. select DM_PCI
  1502. select DM_RNG
  1503. select DM_RTC
  1504. select DM_SCSI
  1505. select DM_SERIAL
  1506. select DM_SPI
  1507. select DM_USB
  1508. select GPIO_EXTRA_HEADER
  1509. select SPL_DM if SPL
  1510. select SPL_DM_SPI if SPL
  1511. select SPL_DM_SPI_FLASH if SPL
  1512. select SPL_DM_I2C if SPL
  1513. select SPL_DM_MMC if SPL
  1514. select SPL_DM_SERIAL if SPL
  1515. help
  1516. Support for Kontron SMARC-sAL28 board.
  1517. config TARGET_COLIBRI_PXA270
  1518. bool "Support colibri_pxa270"
  1519. select CPU_PXA
  1520. select GPIO_EXTRA_HEADER
  1521. config ARCH_UNIPHIER
  1522. bool "Socionext UniPhier SoCs"
  1523. select BOARD_LATE_INIT
  1524. select DM
  1525. select DM_ETH
  1526. select DM_GPIO
  1527. select DM_I2C
  1528. select DM_MMC
  1529. select DM_MTD
  1530. select DM_RESET
  1531. select DM_SERIAL
  1532. select DM_USB
  1533. select OF_BOARD_SETUP
  1534. select OF_CONTROL
  1535. select OF_LIBFDT
  1536. select PINCTRL
  1537. select SPL_BOARD_INIT if SPL
  1538. select SPL_DM if SPL
  1539. select SPL_LIBCOMMON_SUPPORT if SPL
  1540. select SPL_LIBGENERIC_SUPPORT if SPL
  1541. select SPL_OF_CONTROL if SPL
  1542. select SPL_PINCTRL if SPL
  1543. select SUPPORT_SPL
  1544. imply CMD_DM
  1545. imply DISTRO_DEFAULTS
  1546. imply FAT_WRITE
  1547. help
  1548. Support for UniPhier SoC family developed by Socionext Inc.
  1549. (formerly, System LSI Business Division of Panasonic Corporation)
  1550. config ARCH_SYNQUACER
  1551. bool "Socionext SynQuacer SoCs"
  1552. select ARM64
  1553. select DM
  1554. select GIC_V3
  1555. select PSCI_RESET
  1556. select SYSRESET
  1557. select SYSRESET_PSCI
  1558. select OF_CONTROL
  1559. help
  1560. Support for SynQuacer SoC family developed by Socionext Inc.
  1561. This SoC is used on 96boards EE DeveloperBox.
  1562. config ARCH_STM32
  1563. bool "Support STMicroelectronics STM32 MCU with cortex M"
  1564. select CPU_V7M
  1565. select DM
  1566. select DM_SERIAL
  1567. select GPIO_EXTRA_HEADER
  1568. imply CMD_DM
  1569. config ARCH_STI
  1570. bool "Support STMicrolectronics SoCs"
  1571. select BLK
  1572. select CPU_V7A
  1573. select DM
  1574. select DM_MMC
  1575. select DM_RESET
  1576. select DM_SERIAL
  1577. imply CMD_DM
  1578. help
  1579. Support for STMicroelectronics STiH407/10 SoC family.
  1580. This SoC is used on Linaro 96Board STiH410-B2260
  1581. config ARCH_STM32MP
  1582. bool "Support STMicroelectronics STM32MP Socs with cortex A"
  1583. select ARCH_MISC_INIT
  1584. select ARCH_SUPPORT_TFABOOT
  1585. select BOARD_LATE_INIT
  1586. select CLK
  1587. select DM
  1588. select DM_GPIO
  1589. select DM_RESET
  1590. select DM_SERIAL
  1591. select GPIO_EXTRA_HEADER
  1592. select MISC
  1593. select OF_CONTROL
  1594. select OF_LIBFDT
  1595. select OF_SYSTEM_SETUP
  1596. select PINCTRL
  1597. select REGMAP
  1598. select SUPPORT_SPL
  1599. select SYSCON
  1600. select SYSRESET
  1601. select SYS_THUMB_BUILD
  1602. imply SPL_SYSRESET
  1603. imply CMD_DM
  1604. imply CMD_POWEROFF
  1605. imply OF_LIBFDT_OVERLAY
  1606. imply ENV_VARS_UBOOT_RUNTIME_CONFIG
  1607. imply USE_PREBOOT
  1608. help
  1609. Support for STM32MP SoC family developed by STMicroelectronics,
  1610. MPUs based on ARM cortex A core
  1611. U-BOOT is running in DDR, loaded by the First Stage BootLoader (FSBL).
  1612. FSBL can be TF-A: Trusted Firmware for Cortex A, for trusted boot
  1613. chain.
  1614. SPL is the unsecure FSBL for the basic boot chain.
  1615. config ARCH_ROCKCHIP
  1616. bool "Support Rockchip SoCs"
  1617. select BLK
  1618. select BINMAN if SPL_OPTEE
  1619. select DM
  1620. select DM_GPIO
  1621. select DM_I2C
  1622. select DM_MMC
  1623. select DM_PWM
  1624. select DM_REGULATOR
  1625. select DM_SERIAL
  1626. select DM_SPI
  1627. select DM_SPI_FLASH
  1628. select DM_USB if USB
  1629. select ENABLE_ARM_SOC_BOOT0_HOOK
  1630. select OF_CONTROL
  1631. select SPI
  1632. select SPL_DM if SPL
  1633. select SPL_DM_SPI if SPL
  1634. select SPL_DM_SPI_FLASH if SPL
  1635. select SYS_MALLOC_F
  1636. select SYS_THUMB_BUILD if !ARM64
  1637. imply ADC
  1638. imply CMD_DM
  1639. imply DEBUG_UART_BOARD_INIT
  1640. imply DISTRO_DEFAULTS
  1641. imply FAT_WRITE
  1642. imply SARADC_ROCKCHIP
  1643. imply SPL_SYSRESET
  1644. imply SPL_SYS_MALLOC_SIMPLE
  1645. imply SYS_NS16550
  1646. imply TPL_SYSRESET
  1647. imply USB_FUNCTION_FASTBOOT
  1648. config ARCH_OCTEONTX
  1649. bool "Support OcteonTX SoCs"
  1650. select CLK
  1651. select DM
  1652. select GPIO_EXTRA_HEADER
  1653. select ARM64
  1654. select OF_CONTROL
  1655. select OF_LIVE
  1656. select BOARD_LATE_INIT
  1657. select SYS_CACHE_SHIFT_7
  1658. config ARCH_OCTEONTX2
  1659. bool "Support OcteonTX2 SoCs"
  1660. select CLK
  1661. select DM
  1662. select GPIO_EXTRA_HEADER
  1663. select ARM64
  1664. select OF_CONTROL
  1665. select OF_LIVE
  1666. select BOARD_LATE_INIT
  1667. select SYS_CACHE_SHIFT_7
  1668. config TARGET_THUNDERX_88XX
  1669. bool "Support ThunderX 88xx"
  1670. select ARM64
  1671. select GPIO_EXTRA_HEADER
  1672. select OF_CONTROL
  1673. select PL01X_SERIAL
  1674. select SYS_CACHE_SHIFT_7
  1675. config ARCH_ASPEED
  1676. bool "Support Aspeed SoCs"
  1677. select DM
  1678. select OF_CONTROL
  1679. imply CMD_DM
  1680. config TARGET_DURIAN
  1681. bool "Support Phytium Durian Platform"
  1682. select ARM64
  1683. select GPIO_EXTRA_HEADER
  1684. help
  1685. Support for durian platform.
  1686. It has 2GB Sdram, uart and pcie.
  1687. config TARGET_PRESIDIO_ASIC
  1688. bool "Support Cortina Presidio ASIC Platform"
  1689. select ARM64
  1690. config TARGET_XENGUEST_ARM64
  1691. bool "Xen guest ARM64"
  1692. select ARM64
  1693. select XEN
  1694. select OF_CONTROL
  1695. select LINUX_KERNEL_IMAGE_HEADER
  1696. select XEN_SERIAL
  1697. select SSCANF
  1698. endchoice
  1699. config ARCH_SUPPORT_TFABOOT
  1700. bool
  1701. config TFABOOT
  1702. bool "Support for booting from TF-A"
  1703. depends on ARCH_SUPPORT_TFABOOT
  1704. default n
  1705. help
  1706. Some platforms support the setup of secure registers (for instance
  1707. for CPU errata handling) or provide secure services like PSCI.
  1708. Those services could also be provided by other firmware parts
  1709. like TF-A (Trusted Firmware for Cortex-A), in which case U-Boot
  1710. does not need to (and cannot) execute this code.
  1711. Enabling this option will make a U-Boot binary that is relying
  1712. on other firmware layers to provide secure functionality.
  1713. config TI_SECURE_DEVICE
  1714. bool "HS Device Type Support"
  1715. depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
  1716. help
  1717. If a high secure (HS) device type is being used, this config
  1718. must be set. This option impacts various aspects of the
  1719. build system (to create signed boot images that can be
  1720. authenticated) and the code. See the doc/README.ti-secure
  1721. file for further details.
  1722. if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE
  1723. config ISW_ENTRY_ADDR
  1724. hex "Address in memory or XIP address of bootloader entry point"
  1725. default 0x402F4000 if AM43XX
  1726. default 0x402F0400 if AM33XX
  1727. default 0x40301350 if OMAP54XX
  1728. help
  1729. After any reset, the boot ROM searches the boot media for a valid
  1730. boot image. For non-XIP devices, the ROM then copies the image into
  1731. internal memory. For all boot modes, after the ROM processes the
  1732. boot image it eventually computes the entry point address depending
  1733. on the device type (secure/non-secure), boot media (xip/non-xip) and
  1734. image headers.
  1735. endif
  1736. source "arch/arm/mach-aspeed/Kconfig"
  1737. source "arch/arm/mach-at91/Kconfig"
  1738. source "arch/arm/mach-bcm283x/Kconfig"
  1739. source "arch/arm/mach-bcmstb/Kconfig"
  1740. source "arch/arm/mach-davinci/Kconfig"
  1741. source "arch/arm/mach-exynos/Kconfig"
  1742. source "arch/arm/mach-highbank/Kconfig"
  1743. source "arch/arm/mach-integrator/Kconfig"
  1744. source "arch/arm/mach-ipq40xx/Kconfig"
  1745. source "arch/arm/mach-k3/Kconfig"
  1746. source "arch/arm/mach-keystone/Kconfig"
  1747. source "arch/arm/mach-kirkwood/Kconfig"
  1748. source "arch/arm/mach-lpc32xx/Kconfig"
  1749. source "arch/arm/mach-mvebu/Kconfig"
  1750. source "arch/arm/mach-octeontx/Kconfig"
  1751. source "arch/arm/mach-octeontx2/Kconfig"
  1752. source "arch/arm/cpu/armv7/ls102xa/Kconfig"
  1753. source "arch/arm/mach-imx/mx2/Kconfig"
  1754. source "arch/arm/mach-imx/mx3/Kconfig"
  1755. source "arch/arm/mach-imx/mx5/Kconfig"
  1756. source "arch/arm/mach-imx/mx6/Kconfig"
  1757. source "arch/arm/mach-imx/mx7/Kconfig"
  1758. source "arch/arm/mach-imx/mx7ulp/Kconfig"
  1759. source "arch/arm/mach-imx/imx8/Kconfig"
  1760. source "arch/arm/mach-imx/imx8m/Kconfig"
  1761. source "arch/arm/mach-imx/imxrt/Kconfig"
  1762. source "arch/arm/mach-imx/mxs/Kconfig"
  1763. source "arch/arm/mach-omap2/Kconfig"
  1764. source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
  1765. source "arch/arm/mach-orion5x/Kconfig"
  1766. source "arch/arm/mach-owl/Kconfig"
  1767. source "arch/arm/mach-rmobile/Kconfig"
  1768. source "arch/arm/mach-meson/Kconfig"
  1769. source "arch/arm/mach-mediatek/Kconfig"
  1770. source "arch/arm/mach-qemu/Kconfig"
  1771. source "arch/arm/mach-rockchip/Kconfig"
  1772. source "arch/arm/mach-s5pc1xx/Kconfig"
  1773. source "arch/arm/mach-snapdragon/Kconfig"
  1774. source "arch/arm/mach-socfpga/Kconfig"
  1775. source "arch/arm/mach-sti/Kconfig"
  1776. source "arch/arm/mach-stm32/Kconfig"
  1777. source "arch/arm/mach-stm32mp/Kconfig"
  1778. source "arch/arm/mach-sunxi/Kconfig"
  1779. source "arch/arm/mach-tegra/Kconfig"
  1780. source "arch/arm/mach-u8500/Kconfig"
  1781. source "arch/arm/mach-uniphier/Kconfig"
  1782. source "arch/arm/cpu/armv7/vf610/Kconfig"
  1783. source "arch/arm/mach-zynq/Kconfig"
  1784. source "arch/arm/mach-zynqmp/Kconfig"
  1785. source "arch/arm/mach-versal/Kconfig"
  1786. source "arch/arm/mach-zynqmp-r5/Kconfig"
  1787. source "arch/arm/cpu/armv7/Kconfig"
  1788. source "arch/arm/cpu/armv8/Kconfig"
  1789. source "arch/arm/mach-imx/Kconfig"
  1790. source "arch/arm/mach-nexell/Kconfig"
  1791. source "board/armltd/total_compute/Kconfig"
  1792. source "board/bosch/shc/Kconfig"
  1793. source "board/bosch/guardian/Kconfig"
  1794. source "board/CarMediaLab/flea3/Kconfig"
  1795. source "board/Marvell/aspenite/Kconfig"
  1796. source "board/Marvell/octeontx/Kconfig"
  1797. source "board/Marvell/octeontx2/Kconfig"
  1798. source "board/armltd/vexpress64/Kconfig"
  1799. source "board/cortina/presidio-asic/Kconfig"
  1800. source "board/broadcom/bcm963158/Kconfig"
  1801. source "board/broadcom/bcm968360bg/Kconfig"
  1802. source "board/broadcom/bcm968580xref/Kconfig"
  1803. source "board/broadcom/bcmns3/Kconfig"
  1804. source "board/cavium/thunderx/Kconfig"
  1805. source "board/eets/pdu001/Kconfig"
  1806. source "board/emulation/qemu-arm/Kconfig"
  1807. source "board/freescale/ls2080aqds/Kconfig"
  1808. source "board/freescale/ls2080ardb/Kconfig"
  1809. source "board/freescale/ls1088a/Kconfig"
  1810. source "board/freescale/ls1028a/Kconfig"
  1811. source "board/freescale/ls1021aqds/Kconfig"
  1812. source "board/freescale/ls1043aqds/Kconfig"
  1813. source "board/freescale/ls1021atwr/Kconfig"
  1814. source "board/freescale/ls1021atsn/Kconfig"
  1815. source "board/freescale/ls1021aiot/Kconfig"
  1816. source "board/freescale/ls1046aqds/Kconfig"
  1817. source "board/freescale/ls1043ardb/Kconfig"
  1818. source "board/freescale/ls1046ardb/Kconfig"
  1819. source "board/freescale/ls1046afrwy/Kconfig"
  1820. source "board/freescale/ls1012aqds/Kconfig"
  1821. source "board/freescale/ls1012ardb/Kconfig"
  1822. source "board/freescale/ls1012afrdm/Kconfig"
  1823. source "board/freescale/lx2160a/Kconfig"
  1824. source "board/grinn/chiliboard/Kconfig"
  1825. source "board/hisilicon/hikey/Kconfig"
  1826. source "board/hisilicon/hikey960/Kconfig"
  1827. source "board/hisilicon/poplar/Kconfig"
  1828. source "board/isee/igep003x/Kconfig"
  1829. source "board/kontron/sl28/Kconfig"
  1830. source "board/myir/mys_6ulx/Kconfig"
  1831. source "board/seeed/npi_imx6ull/Kconfig"
  1832. source "board/socionext/developerbox/Kconfig"
  1833. source "board/st/stv0991/Kconfig"
  1834. source "board/tcl/sl50/Kconfig"
  1835. source "board/toradex/colibri_pxa270/Kconfig"
  1836. source "board/variscite/dart_6ul/Kconfig"
  1837. source "board/vscom/baltos/Kconfig"
  1838. source "board/phytium/durian/Kconfig"
  1839. source "board/xen/xenguest_arm64/Kconfig"
  1840. source "board/keymile/Kconfig"
  1841. source "arch/arm/Kconfig.debug"
  1842. endmenu
  1843. config SPL_LDSCRIPT
  1844. default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK
  1845. default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
  1846. default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64