omap3_spi.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Jagan Teki <jteki@openedev.com>
  4. * Christophe Ricard <christophe.ricard@gmail.com>
  5. *
  6. * Copyright (C) 2010 Dirk Behme <dirk.behme@googlemail.com>
  7. *
  8. * Driver for McSPI controller on OMAP3. Based on davinci_spi.c
  9. * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
  10. *
  11. * Copyright (C) 2007 Atmel Corporation
  12. *
  13. * Parts taken from linux/drivers/spi/omap2_mcspi.c
  14. * Copyright (C) 2005, 2006 Nokia Corporation
  15. *
  16. * Modified by Ruslan Araslanov <ruslan.araslanov@vitecmm.com>
  17. */
  18. #include <common.h>
  19. #include <dm.h>
  20. #include <spi.h>
  21. #include <malloc.h>
  22. #include <asm/io.h>
  23. #include <linux/bitops.h>
  24. DECLARE_GLOBAL_DATA_PTR;
  25. #if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
  26. #define OMAP3_MCSPI1_BASE 0x48030100
  27. #define OMAP3_MCSPI2_BASE 0x481A0100
  28. #else
  29. #define OMAP3_MCSPI1_BASE 0x48098000
  30. #define OMAP3_MCSPI2_BASE 0x4809A000
  31. #define OMAP3_MCSPI3_BASE 0x480B8000
  32. #define OMAP3_MCSPI4_BASE 0x480BA000
  33. #endif
  34. #define OMAP4_MCSPI_REG_OFFSET 0x100
  35. struct omap2_mcspi_platform_config {
  36. unsigned int regs_offset;
  37. };
  38. /* per-register bitmasks */
  39. #define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
  40. #define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
  41. #define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE BIT(0)
  42. #define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
  43. #define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0)
  44. #define OMAP3_MCSPI_MODULCTRL_SINGLE BIT(0)
  45. #define OMAP3_MCSPI_MODULCTRL_MS BIT(2)
  46. #define OMAP3_MCSPI_MODULCTRL_STEST BIT(3)
  47. #define OMAP3_MCSPI_CHCONF_PHA BIT(0)
  48. #define OMAP3_MCSPI_CHCONF_POL BIT(1)
  49. #define OMAP3_MCSPI_CHCONF_CLKD_MASK GENMASK(5, 2)
  50. #define OMAP3_MCSPI_CHCONF_EPOL BIT(6)
  51. #define OMAP3_MCSPI_CHCONF_WL_MASK GENMASK(11, 7)
  52. #define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
  53. #define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
  54. #define OMAP3_MCSPI_CHCONF_TRM_MASK GENMASK(13, 12)
  55. #define OMAP3_MCSPI_CHCONF_DMAW BIT(14)
  56. #define OMAP3_MCSPI_CHCONF_DMAR BIT(15)
  57. #define OMAP3_MCSPI_CHCONF_DPE0 BIT(16)
  58. #define OMAP3_MCSPI_CHCONF_DPE1 BIT(17)
  59. #define OMAP3_MCSPI_CHCONF_IS BIT(18)
  60. #define OMAP3_MCSPI_CHCONF_TURBO BIT(19)
  61. #define OMAP3_MCSPI_CHCONF_FORCE BIT(20)
  62. #define OMAP3_MCSPI_CHSTAT_RXS BIT(0)
  63. #define OMAP3_MCSPI_CHSTAT_TXS BIT(1)
  64. #define OMAP3_MCSPI_CHSTAT_EOT BIT(2)
  65. #define OMAP3_MCSPI_CHCTRL_EN BIT(0)
  66. #define OMAP3_MCSPI_CHCTRL_DIS (0 << 0)
  67. #define OMAP3_MCSPI_WAKEUPENABLE_WKEN BIT(0)
  68. #define MCSPI_PINDIR_D0_IN_D1_OUT 0
  69. #define MCSPI_PINDIR_D0_OUT_D1_IN 1
  70. #define OMAP3_MCSPI_MAX_FREQ 48000000
  71. #define SPI_WAIT_TIMEOUT 10
  72. /* OMAP3 McSPI registers */
  73. struct mcspi_channel {
  74. unsigned int chconf; /* 0x2C, 0x40, 0x54, 0x68 */
  75. unsigned int chstat; /* 0x30, 0x44, 0x58, 0x6C */
  76. unsigned int chctrl; /* 0x34, 0x48, 0x5C, 0x70 */
  77. unsigned int tx; /* 0x38, 0x4C, 0x60, 0x74 */
  78. unsigned int rx; /* 0x3C, 0x50, 0x64, 0x78 */
  79. };
  80. struct mcspi {
  81. unsigned char res1[0x10];
  82. unsigned int sysconfig; /* 0x10 */
  83. unsigned int sysstatus; /* 0x14 */
  84. unsigned int irqstatus; /* 0x18 */
  85. unsigned int irqenable; /* 0x1C */
  86. unsigned int wakeupenable; /* 0x20 */
  87. unsigned int syst; /* 0x24 */
  88. unsigned int modulctrl; /* 0x28 */
  89. struct mcspi_channel channel[4];
  90. /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
  91. /* channel1: 0x40 - 0x50, bus 0 & 1 */
  92. /* channel2: 0x54 - 0x64, bus 0 & 1 */
  93. /* channel3: 0x68 - 0x78, bus 0 */
  94. };
  95. struct omap3_spi_priv {
  96. #if !CONFIG_IS_ENABLED(DM_SPI)
  97. struct spi_slave slave;
  98. #endif
  99. struct mcspi *regs;
  100. unsigned int cs;
  101. unsigned int freq;
  102. unsigned int mode;
  103. unsigned int wordlen;
  104. unsigned int pin_dir:1;
  105. };
  106. static void omap3_spi_write_chconf(struct omap3_spi_priv *priv, int val)
  107. {
  108. writel(val, &priv->regs->channel[priv->cs].chconf);
  109. /* Flash post writes to make immediate effect */
  110. readl(&priv->regs->channel[priv->cs].chconf);
  111. }
  112. static void omap3_spi_set_enable(struct omap3_spi_priv *priv, int enable)
  113. {
  114. writel(enable, &priv->regs->channel[priv->cs].chctrl);
  115. /* Flash post writes to make immediate effect */
  116. readl(&priv->regs->channel[priv->cs].chctrl);
  117. }
  118. static int omap3_spi_write(struct omap3_spi_priv *priv, unsigned int len,
  119. const void *txp, unsigned long flags)
  120. {
  121. ulong start;
  122. int i, chconf;
  123. chconf = readl(&priv->regs->channel[priv->cs].chconf);
  124. /* Enable the channel */
  125. omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN);
  126. chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
  127. chconf |= (priv->wordlen - 1) << 7;
  128. chconf |= OMAP3_MCSPI_CHCONF_TRM_TX_ONLY;
  129. chconf |= OMAP3_MCSPI_CHCONF_FORCE;
  130. omap3_spi_write_chconf(priv, chconf);
  131. for (i = 0; i < len; i++) {
  132. /* wait till TX register is empty (TXS == 1) */
  133. start = get_timer(0);
  134. while (!(readl(&priv->regs->channel[priv->cs].chstat) &
  135. OMAP3_MCSPI_CHSTAT_TXS)) {
  136. if (get_timer(start) > SPI_WAIT_TIMEOUT) {
  137. printf("SPI TXS timed out, status=0x%08x\n",
  138. readl(&priv->regs->channel[priv->cs].chstat));
  139. return -1;
  140. }
  141. }
  142. /* Write the data */
  143. unsigned int *tx = &priv->regs->channel[priv->cs].tx;
  144. if (priv->wordlen > 16)
  145. writel(((u32 *)txp)[i], tx);
  146. else if (priv->wordlen > 8)
  147. writel(((u16 *)txp)[i], tx);
  148. else
  149. writel(((u8 *)txp)[i], tx);
  150. }
  151. /* wait to finish of transfer */
  152. while ((readl(&priv->regs->channel[priv->cs].chstat) &
  153. (OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS)) !=
  154. (OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS))
  155. ;
  156. /* Disable the channel otherwise the next immediate RX will get affected */
  157. omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);
  158. if (flags & SPI_XFER_END) {
  159. chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
  160. omap3_spi_write_chconf(priv, chconf);
  161. }
  162. return 0;
  163. }
  164. static int omap3_spi_read(struct omap3_spi_priv *priv, unsigned int len,
  165. void *rxp, unsigned long flags)
  166. {
  167. int i, chconf;
  168. ulong start;
  169. chconf = readl(&priv->regs->channel[priv->cs].chconf);
  170. /* Enable the channel */
  171. omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN);
  172. chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
  173. chconf |= (priv->wordlen - 1) << 7;
  174. chconf |= OMAP3_MCSPI_CHCONF_TRM_RX_ONLY;
  175. chconf |= OMAP3_MCSPI_CHCONF_FORCE;
  176. omap3_spi_write_chconf(priv, chconf);
  177. writel(0, &priv->regs->channel[priv->cs].tx);
  178. for (i = 0; i < len; i++) {
  179. start = get_timer(0);
  180. /* Wait till RX register contains data (RXS == 1) */
  181. while (!(readl(&priv->regs->channel[priv->cs].chstat) &
  182. OMAP3_MCSPI_CHSTAT_RXS)) {
  183. if (get_timer(start) > SPI_WAIT_TIMEOUT) {
  184. printf("SPI RXS timed out, status=0x%08x\n",
  185. readl(&priv->regs->channel[priv->cs].chstat));
  186. return -1;
  187. }
  188. }
  189. /* Disable the channel to prevent furher receiving */
  190. if (i == (len - 1))
  191. omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);
  192. /* Read the data */
  193. unsigned int *rx = &priv->regs->channel[priv->cs].rx;
  194. if (priv->wordlen > 16)
  195. ((u32 *)rxp)[i] = readl(rx);
  196. else if (priv->wordlen > 8)
  197. ((u16 *)rxp)[i] = (u16)readl(rx);
  198. else
  199. ((u8 *)rxp)[i] = (u8)readl(rx);
  200. }
  201. if (flags & SPI_XFER_END) {
  202. chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
  203. omap3_spi_write_chconf(priv, chconf);
  204. }
  205. return 0;
  206. }
  207. /*McSPI Transmit Receive Mode*/
  208. static int omap3_spi_txrx(struct omap3_spi_priv *priv, unsigned int len,
  209. const void *txp, void *rxp, unsigned long flags)
  210. {
  211. ulong start;
  212. int chconf, i = 0;
  213. chconf = readl(&priv->regs->channel[priv->cs].chconf);
  214. /*Enable SPI channel*/
  215. omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN);
  216. /*set TRANSMIT-RECEIVE Mode*/
  217. chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
  218. chconf |= (priv->wordlen - 1) << 7;
  219. chconf |= OMAP3_MCSPI_CHCONF_FORCE;
  220. omap3_spi_write_chconf(priv, chconf);
  221. /*Shift in and out 1 byte at time*/
  222. for (i=0; i < len; i++){
  223. /* Write: wait for TX empty (TXS == 1)*/
  224. start = get_timer(0);
  225. while (!(readl(&priv->regs->channel[priv->cs].chstat) &
  226. OMAP3_MCSPI_CHSTAT_TXS)) {
  227. if (get_timer(start) > SPI_WAIT_TIMEOUT) {
  228. printf("SPI TXS timed out, status=0x%08x\n",
  229. readl(&priv->regs->channel[priv->cs].chstat));
  230. return -1;
  231. }
  232. }
  233. /* Write the data */
  234. unsigned int *tx = &priv->regs->channel[priv->cs].tx;
  235. if (priv->wordlen > 16)
  236. writel(((u32 *)txp)[i], tx);
  237. else if (priv->wordlen > 8)
  238. writel(((u16 *)txp)[i], tx);
  239. else
  240. writel(((u8 *)txp)[i], tx);
  241. /*Read: wait for RX containing data (RXS == 1)*/
  242. start = get_timer(0);
  243. while (!(readl(&priv->regs->channel[priv->cs].chstat) &
  244. OMAP3_MCSPI_CHSTAT_RXS)) {
  245. if (get_timer(start) > SPI_WAIT_TIMEOUT) {
  246. printf("SPI RXS timed out, status=0x%08x\n",
  247. readl(&priv->regs->channel[priv->cs].chstat));
  248. return -1;
  249. }
  250. }
  251. /* Read the data */
  252. unsigned int *rx = &priv->regs->channel[priv->cs].rx;
  253. if (priv->wordlen > 16)
  254. ((u32 *)rxp)[i] = readl(rx);
  255. else if (priv->wordlen > 8)
  256. ((u16 *)rxp)[i] = (u16)readl(rx);
  257. else
  258. ((u8 *)rxp)[i] = (u8)readl(rx);
  259. }
  260. /* Disable the channel */
  261. omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);
  262. /*if transfer must be terminated disable the channel*/
  263. if (flags & SPI_XFER_END) {
  264. chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
  265. omap3_spi_write_chconf(priv, chconf);
  266. }
  267. return 0;
  268. }
  269. static int _spi_xfer(struct omap3_spi_priv *priv, unsigned int bitlen,
  270. const void *dout, void *din, unsigned long flags)
  271. {
  272. unsigned int len;
  273. int ret = -1;
  274. if (priv->wordlen < 4 || priv->wordlen > 32) {
  275. printf("omap3_spi: invalid wordlen %d\n", priv->wordlen);
  276. return -1;
  277. }
  278. if (bitlen % priv->wordlen)
  279. return -1;
  280. len = bitlen / priv->wordlen;
  281. if (bitlen == 0) { /* only change CS */
  282. int chconf = readl(&priv->regs->channel[priv->cs].chconf);
  283. if (flags & SPI_XFER_BEGIN) {
  284. omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN);
  285. chconf |= OMAP3_MCSPI_CHCONF_FORCE;
  286. omap3_spi_write_chconf(priv, chconf);
  287. }
  288. if (flags & SPI_XFER_END) {
  289. chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
  290. omap3_spi_write_chconf(priv, chconf);
  291. omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);
  292. }
  293. ret = 0;
  294. } else {
  295. if (dout != NULL && din != NULL)
  296. ret = omap3_spi_txrx(priv, len, dout, din, flags);
  297. else if (dout != NULL)
  298. ret = omap3_spi_write(priv, len, dout, flags);
  299. else if (din != NULL)
  300. ret = omap3_spi_read(priv, len, din, flags);
  301. }
  302. return ret;
  303. }
  304. static void _omap3_spi_set_speed(struct omap3_spi_priv *priv)
  305. {
  306. uint32_t confr, div = 0;
  307. confr = readl(&priv->regs->channel[priv->cs].chconf);
  308. /* Calculate clock divisor. Valid range: 0x0 - 0xC ( /1 - /4096 ) */
  309. if (priv->freq) {
  310. while (div <= 0xC && (OMAP3_MCSPI_MAX_FREQ / (1 << div))
  311. > priv->freq)
  312. div++;
  313. } else {
  314. div = 0xC;
  315. }
  316. /* set clock divisor */
  317. confr &= ~OMAP3_MCSPI_CHCONF_CLKD_MASK;
  318. confr |= div << 2;
  319. omap3_spi_write_chconf(priv, confr);
  320. }
  321. static void _omap3_spi_set_mode(struct omap3_spi_priv *priv)
  322. {
  323. uint32_t confr;
  324. confr = readl(&priv->regs->channel[priv->cs].chconf);
  325. /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
  326. * REVISIT: this controller could support SPI_3WIRE mode.
  327. */
  328. if (priv->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
  329. confr &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
  330. confr |= OMAP3_MCSPI_CHCONF_DPE0;
  331. } else {
  332. confr &= ~OMAP3_MCSPI_CHCONF_DPE0;
  333. confr |= OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1;
  334. }
  335. /* set SPI mode 0..3 */
  336. confr &= ~(OMAP3_MCSPI_CHCONF_POL | OMAP3_MCSPI_CHCONF_PHA);
  337. if (priv->mode & SPI_CPHA)
  338. confr |= OMAP3_MCSPI_CHCONF_PHA;
  339. if (priv->mode & SPI_CPOL)
  340. confr |= OMAP3_MCSPI_CHCONF_POL;
  341. /* set chipselect polarity; manage with FORCE */
  342. if (!(priv->mode & SPI_CS_HIGH))
  343. confr |= OMAP3_MCSPI_CHCONF_EPOL; /* active-low; normal */
  344. else
  345. confr &= ~OMAP3_MCSPI_CHCONF_EPOL;
  346. /* Transmit & receive mode */
  347. confr &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
  348. omap3_spi_write_chconf(priv, confr);
  349. }
  350. static void _omap3_spi_set_wordlen(struct omap3_spi_priv *priv)
  351. {
  352. unsigned int confr;
  353. /* McSPI individual channel configuration */
  354. confr = readl(&priv->regs->channel[priv->cs].chconf);
  355. /* wordlength */
  356. confr &= ~OMAP3_MCSPI_CHCONF_WL_MASK;
  357. confr |= (priv->wordlen - 1) << 7;
  358. omap3_spi_write_chconf(priv, confr);
  359. }
  360. static void spi_reset(struct mcspi *regs)
  361. {
  362. unsigned int tmp;
  363. writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET, &regs->sysconfig);
  364. do {
  365. tmp = readl(&regs->sysstatus);
  366. } while (!(tmp & OMAP3_MCSPI_SYSSTATUS_RESETDONE));
  367. writel(OMAP3_MCSPI_SYSCONFIG_AUTOIDLE |
  368. OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP |
  369. OMAP3_MCSPI_SYSCONFIG_SMARTIDLE, &regs->sysconfig);
  370. writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, &regs->wakeupenable);
  371. }
  372. static void _omap3_spi_claim_bus(struct omap3_spi_priv *priv)
  373. {
  374. unsigned int conf;
  375. /*
  376. * setup when switching from (reset default) slave mode
  377. * to single-channel master mode
  378. */
  379. conf = readl(&priv->regs->modulctrl);
  380. conf &= ~(OMAP3_MCSPI_MODULCTRL_STEST | OMAP3_MCSPI_MODULCTRL_MS);
  381. conf |= OMAP3_MCSPI_MODULCTRL_SINGLE;
  382. writel(conf, &priv->regs->modulctrl);
  383. }
  384. #if !CONFIG_IS_ENABLED(DM_SPI)
  385. static inline struct omap3_spi_priv *to_omap3_spi(struct spi_slave *slave)
  386. {
  387. return container_of(slave, struct omap3_spi_priv, slave);
  388. }
  389. void spi_free_slave(struct spi_slave *slave)
  390. {
  391. struct omap3_spi_priv *priv = to_omap3_spi(slave);
  392. free(priv);
  393. }
  394. int spi_claim_bus(struct spi_slave *slave)
  395. {
  396. struct omap3_spi_priv *priv = to_omap3_spi(slave);
  397. spi_reset(priv->regs);
  398. _omap3_spi_claim_bus(priv);
  399. _omap3_spi_set_wordlen(priv);
  400. _omap3_spi_set_mode(priv);
  401. _omap3_spi_set_speed(priv);
  402. return 0;
  403. }
  404. void spi_release_bus(struct spi_slave *slave)
  405. {
  406. struct omap3_spi_priv *priv = to_omap3_spi(slave);
  407. writel(OMAP3_MCSPI_MODULCTRL_MS, &priv->regs->modulctrl);
  408. }
  409. struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
  410. unsigned int max_hz, unsigned int mode)
  411. {
  412. struct omap3_spi_priv *priv;
  413. struct mcspi *regs;
  414. /*
  415. * OMAP3 McSPI (MultiChannel SPI) has 4 busses (modules)
  416. * with different number of chip selects (CS, channels):
  417. * McSPI1 has 4 CS (bus 0, cs 0 - 3)
  418. * McSPI2 has 2 CS (bus 1, cs 0 - 1)
  419. * McSPI3 has 2 CS (bus 2, cs 0 - 1)
  420. * McSPI4 has 1 CS (bus 3, cs 0)
  421. */
  422. switch (bus) {
  423. case 0:
  424. regs = (struct mcspi *)OMAP3_MCSPI1_BASE;
  425. break;
  426. #ifdef OMAP3_MCSPI2_BASE
  427. case 1:
  428. regs = (struct mcspi *)OMAP3_MCSPI2_BASE;
  429. break;
  430. #endif
  431. #ifdef OMAP3_MCSPI3_BASE
  432. case 2:
  433. regs = (struct mcspi *)OMAP3_MCSPI3_BASE;
  434. break;
  435. #endif
  436. #ifdef OMAP3_MCSPI4_BASE
  437. case 3:
  438. regs = (struct mcspi *)OMAP3_MCSPI4_BASE;
  439. break;
  440. #endif
  441. default:
  442. printf("SPI error: unsupported bus %i. Supported busses 0 - 3\n", bus);
  443. return NULL;
  444. }
  445. if (((bus == 0) && (cs > 3)) ||
  446. ((bus == 1) && (cs > 1)) ||
  447. ((bus == 2) && (cs > 1)) ||
  448. ((bus == 3) && (cs > 0))) {
  449. printf("SPI error: unsupported chip select %i on bus %i\n", cs, bus);
  450. return NULL;
  451. }
  452. if (max_hz > OMAP3_MCSPI_MAX_FREQ) {
  453. printf("SPI error: unsupported frequency %i Hz. Max frequency is 48 MHz\n",
  454. max_hz);
  455. return NULL;
  456. }
  457. if (mode > SPI_MODE_3) {
  458. printf("SPI error: unsupported SPI mode %i\n", mode);
  459. return NULL;
  460. }
  461. priv = spi_alloc_slave(struct omap3_spi_priv, bus, cs);
  462. if (!priv) {
  463. printf("SPI error: malloc of SPI structure failed\n");
  464. return NULL;
  465. }
  466. priv->regs = regs;
  467. priv->cs = cs;
  468. priv->freq = max_hz;
  469. priv->mode = mode;
  470. priv->wordlen = priv->slave.wordlen;
  471. #if 0
  472. /* Please migrate to DM_SPI support for this feature. */
  473. priv->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
  474. #endif
  475. return &priv->slave;
  476. }
  477. int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
  478. const void *dout, void *din, unsigned long flags)
  479. {
  480. struct omap3_spi_priv *priv = to_omap3_spi(slave);
  481. return _spi_xfer(priv, bitlen, dout, din, flags);
  482. }
  483. #else
  484. static int omap3_spi_claim_bus(struct udevice *dev)
  485. {
  486. struct udevice *bus = dev->parent;
  487. struct omap3_spi_priv *priv = dev_get_priv(bus);
  488. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  489. priv->cs = slave_plat->cs;
  490. priv->freq = slave_plat->max_hz;
  491. _omap3_spi_claim_bus(priv);
  492. return 0;
  493. }
  494. static int omap3_spi_release_bus(struct udevice *dev)
  495. {
  496. struct udevice *bus = dev->parent;
  497. struct omap3_spi_priv *priv = dev_get_priv(bus);
  498. writel(OMAP3_MCSPI_MODULCTRL_MS, &priv->regs->modulctrl);
  499. return 0;
  500. }
  501. static int omap3_spi_set_wordlen(struct udevice *dev, unsigned int wordlen)
  502. {
  503. struct udevice *bus = dev->parent;
  504. struct omap3_spi_priv *priv = dev_get_priv(bus);
  505. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  506. priv->cs = slave_plat->cs;
  507. priv->wordlen = wordlen;
  508. _omap3_spi_set_wordlen(priv);
  509. return 0;
  510. }
  511. static int omap3_spi_probe(struct udevice *dev)
  512. {
  513. struct omap3_spi_priv *priv = dev_get_priv(dev);
  514. const void *blob = gd->fdt_blob;
  515. int node = dev_of_offset(dev);
  516. struct omap2_mcspi_platform_config* data =
  517. (struct omap2_mcspi_platform_config*)dev_get_driver_data(dev);
  518. priv->regs = (struct mcspi *)(devfdt_get_addr(dev) + data->regs_offset);
  519. if (fdtdec_get_bool(blob, node, "ti,pindir-d0-out-d1-in"))
  520. priv->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
  521. else
  522. priv->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT;
  523. priv->wordlen = SPI_DEFAULT_WORDLEN;
  524. spi_reset(priv->regs);
  525. return 0;
  526. }
  527. static int omap3_spi_xfer(struct udevice *dev, unsigned int bitlen,
  528. const void *dout, void *din, unsigned long flags)
  529. {
  530. struct udevice *bus = dev->parent;
  531. struct omap3_spi_priv *priv = dev_get_priv(bus);
  532. return _spi_xfer(priv, bitlen, dout, din, flags);
  533. }
  534. static int omap3_spi_set_speed(struct udevice *dev, unsigned int speed)
  535. {
  536. struct omap3_spi_priv *priv = dev_get_priv(dev);
  537. priv->freq = speed;
  538. _omap3_spi_set_speed(priv);
  539. return 0;
  540. }
  541. static int omap3_spi_set_mode(struct udevice *dev, uint mode)
  542. {
  543. struct omap3_spi_priv *priv = dev_get_priv(dev);
  544. priv->mode = mode;
  545. _omap3_spi_set_mode(priv);
  546. return 0;
  547. }
  548. static const struct dm_spi_ops omap3_spi_ops = {
  549. .claim_bus = omap3_spi_claim_bus,
  550. .release_bus = omap3_spi_release_bus,
  551. .set_wordlen = omap3_spi_set_wordlen,
  552. .xfer = omap3_spi_xfer,
  553. .set_speed = omap3_spi_set_speed,
  554. .set_mode = omap3_spi_set_mode,
  555. /*
  556. * cs_info is not needed, since we require all chip selects to be
  557. * in the device tree explicitly
  558. */
  559. };
  560. static struct omap2_mcspi_platform_config omap2_pdata = {
  561. .regs_offset = 0,
  562. };
  563. static struct omap2_mcspi_platform_config omap4_pdata = {
  564. .regs_offset = OMAP4_MCSPI_REG_OFFSET,
  565. };
  566. static const struct udevice_id omap3_spi_ids[] = {
  567. { .compatible = "ti,omap2-mcspi", .data = (ulong)&omap2_pdata },
  568. { .compatible = "ti,omap4-mcspi", .data = (ulong)&omap4_pdata },
  569. { }
  570. };
  571. U_BOOT_DRIVER(omap3_spi) = {
  572. .name = "omap3_spi",
  573. .id = UCLASS_SPI,
  574. .of_match = omap3_spi_ids,
  575. .probe = omap3_spi_probe,
  576. .ops = &omap3_spi_ops,
  577. .priv_auto_alloc_size = sizeof(struct omap3_spi_priv),
  578. };
  579. #endif