init.c 1.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2021 MediaTek Inc.
  4. * Copyright (C) 2021 BayLibre, SAS
  5. * Author: Fabien Parent <fparent@baylibre.com>
  6. */
  7. #include <clk.h>
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <fdtdec.h>
  11. #include <ram.h>
  12. #include <asm/arch/misc.h>
  13. #include <asm/armv8/mmu.h>
  14. #include <asm/sections.h>
  15. #include <asm/system.h>
  16. #include <dm/uclass.h>
  17. #include <dt-bindings/clock/mt8516-clk.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. int dram_init(void)
  20. {
  21. int ret;
  22. ret = fdtdec_setup_memory_banksize();
  23. if (ret)
  24. return ret;
  25. return fdtdec_setup_mem_size_base();
  26. }
  27. int dram_init_banksize(void)
  28. {
  29. gd->bd->bi_dram[0].start = gd->ram_base;
  30. gd->bd->bi_dram[0].size = gd->ram_size;
  31. return 0;
  32. }
  33. int mtk_pll_early_init(void)
  34. {
  35. return 0;
  36. }
  37. int mtk_soc_early_init(void)
  38. {
  39. return 0;
  40. }
  41. void reset_cpu(void)
  42. {
  43. psci_system_reset();
  44. }
  45. int print_cpuinfo(void)
  46. {
  47. printf("CPU: MediaTek MT8183\n");
  48. return 0;
  49. }
  50. static struct mm_region mt8183_mem_map[] = {
  51. {
  52. /* DDR */
  53. .virt = 0x40000000UL,
  54. .phys = 0x40000000UL,
  55. .size = 0x80000000UL,
  56. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
  57. }, {
  58. .virt = 0x00000000UL,
  59. .phys = 0x00000000UL,
  60. .size = 0x20000000UL,
  61. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  62. PTE_BLOCK_NON_SHARE |
  63. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  64. }, {
  65. 0,
  66. }
  67. };
  68. struct mm_region *mem_map = mt8183_mem_map;