lowlevel_init.S 3.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2020 Stefan Roese <sr@denx.de>
  4. */
  5. #include <config.h>
  6. #include <asm-offsets.h>
  7. #include <asm/cacheops.h>
  8. #include <asm/regdef.h>
  9. #include <asm/mipsregs.h>
  10. #include <asm/addrspace.h>
  11. #include <asm/asm.h>
  12. #include <mach/octeon-model.h>
  13. #define COP0_CVMCTL_REG $9,7 /* Cavium control */
  14. #define COP0_CVMMEMCTL_REG $11,7 /* Cavium memory control */
  15. #define COP0_PROC_ID_REG $15,0
  16. .set noreorder
  17. LEAF(lowlevel_init)
  18. /* Set LMEMSZ in CVMMEMCTL register */
  19. dmfc0 a0, COP0_CVMMEMCTL_REG
  20. dins a0, zero, 0, 9
  21. mfc0 a4, COP0_PROC_ID_REG
  22. li a5, OCTEON_CN63XX_PASS1_0 /* Octeon cn63xx pass1 chip id */
  23. bgt a5, a4, 2f
  24. ori a0, 0x104 /* setup 4 lines of scratch */
  25. ori a6, a5, 8 /* Octeon cn63xx pass2 chip id */
  26. bge a4, a6, 2f
  27. nop
  28. li a6, 4
  29. ins a0, a6, 11, 4 /* Set WBTHRESH=4 as per Core-14752 errata */
  30. 2:
  31. dmtc0 a0, COP0_CVMMEMCTL_REG
  32. /* Set REPUN bit in CVMCTL register */
  33. dmfc0 a0, COP0_CVMCTL_REG
  34. ori a0, 1<<14 /* enable fixup of unaligned mem access */
  35. dmtc0 a0, COP0_CVMCTL_REG
  36. jr ra
  37. nop
  38. END(lowlevel_init)
  39. LEAF(mips_mach_early_init)
  40. move s0, ra
  41. bal __dummy
  42. nop
  43. __dummy:
  44. /* Get the actual address that we are running at */
  45. PTR_LA a7, __dummy
  46. dsubu t3, ra, a7 /* t3 now has reloc offset */
  47. PTR_LA t1, _start
  48. daddu t0, t1, t3 /* t0 now has actual address of _start */
  49. /* Calculate end address of copy loop */
  50. PTR_LA t2, _end
  51. daddiu t2, t2, 0x4000 /* Increase size to include appended DTB */
  52. daddiu t2, t2, 127
  53. ins t2, zero, 0, 7 /* Round up to cache line for memcpy */
  54. /* Copy ourself to the L2 cache from flash, 32 bytes at a time */
  55. 1:
  56. ld a0, 0(t0)
  57. ld a1, 8(t0)
  58. ld a2, 16(t0)
  59. ld a3, 24(t0)
  60. sd a0, 0(t1)
  61. sd a1, 8(t1)
  62. sd a2, 16(t1)
  63. sd a3, 24(t1)
  64. addiu t0, 32
  65. addiu t1, 32
  66. bne t1, t2, 1b
  67. nop
  68. sync
  69. /*
  70. * Return to start.S now running from TEXT_BASE, which points
  71. * to DRAM address space, which effectively is L2 cache now.
  72. * This speeds up the init process extremely, especially the
  73. * DDR init code.
  74. */
  75. dsubu s0, s0, t3 /* Fixup return address with reloc offset */
  76. jr.hb s0 /* Jump back with hazard barrier */
  77. nop
  78. END(mips_mach_early_init)
  79. LEAF(nmi_bootvector)
  80. /*
  81. * From Marvell original bootvector setup
  82. */
  83. mfc0 k0, CP0_STATUS
  84. /* Enable 64-bit addressing, set ERL (should already be set) */
  85. ori k0, 0x84
  86. mtc0 k0, CP0_STATUS
  87. /* Core-14345, clear L1 Dcache virtual tags if the core hit an NMI */
  88. cache 17, 0($0)
  89. /*
  90. * Needed for Linux kernel booting, otherwise it hangs while
  91. * zero'ing all of CVMSEG
  92. */
  93. dmfc0 a0, COP0_CVMMEMCTL_REG
  94. dins a0, zero, 0, 9
  95. ori a0, 0x104 /* setup 4 lines of scratch */
  96. dmtc0 a0, COP0_CVMMEMCTL_REG
  97. /*
  98. * Load parameters and entry point
  99. */
  100. PTR_LA t9, nmi_handler_para
  101. sync
  102. ld s0, 0x00(t9)
  103. ld a0, 0x08(t9)
  104. ld a1, 0x10(t9)
  105. ld a2, 0x18(t9)
  106. ld a3, 0x20(t9)
  107. /* Finally jump to entry point (start kernel etc) */
  108. j s0
  109. nop
  110. END(nmi_bootvector)
  111. /*
  112. * Add here some space for the NMI parameters (entry point and args)
  113. */
  114. .globl nmi_handler_para
  115. nmi_handler_para:
  116. .dword 0 // entry-point
  117. .dword 0 // arg0
  118. .dword 0 // arg1
  119. .dword 0 // arg2
  120. .dword 0 // arg3