cvmx-coremask.c 8.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018-2020 Marvell International Ltd.
  4. */
  5. #include <env.h>
  6. #include <errno.h>
  7. #include <linux/compat.h>
  8. #include <linux/ctype.h>
  9. #include <mach/cvmx-regs.h>
  10. #include <mach/cvmx-coremask.h>
  11. #include <mach/cvmx-fuse.h>
  12. #include <mach/octeon-model.h>
  13. #include <mach/octeon-feature.h>
  14. struct cvmx_coremask *get_coremask_override(struct cvmx_coremask *pcm)
  15. {
  16. struct cvmx_coremask pcm_override = CVMX_COREMASK_MAX;
  17. char *cptr;
  18. /* The old code sets the number of cores to be to 16 in this case. */
  19. cvmx_coremask_set_cores(pcm, 0, 16);
  20. if (OCTEON_IS_OCTEON2() || OCTEON_IS_OCTEON3())
  21. cvmx_coremask_copy(pcm, &pcm_override);
  22. cptr = env_get("coremask_override");
  23. if (cptr) {
  24. if (cvmx_coremask_str2bmp(pcm, cptr) < 0)
  25. return NULL;
  26. }
  27. return pcm;
  28. }
  29. /* Validate the coremask that is passed to a boot* function. */
  30. int validate_coremask(struct cvmx_coremask *pcm)
  31. {
  32. struct cvmx_coremask coremask_override;
  33. struct cvmx_coremask fuse_coremask;
  34. if (!get_coremask_override(&coremask_override))
  35. return -1;
  36. octeon_get_available_coremask(&fuse_coremask);
  37. if (!cvmx_coremask_is_subset(&fuse_coremask, pcm)) {
  38. puts("ERROR: Can't boot cores that don't exist!\n");
  39. puts("Available coremask:\n");
  40. cvmx_coremask_print(&fuse_coremask);
  41. return -1;
  42. }
  43. if (!cvmx_coremask_is_subset(&coremask_override, pcm)) {
  44. struct cvmx_coremask print_cm;
  45. puts("Notice: coremask changed from:\n");
  46. cvmx_coremask_print(pcm);
  47. puts("based on coremask_override of:\n");
  48. cvmx_coremask_print(&coremask_override);
  49. cvmx_coremask_and(&print_cm, pcm, &coremask_override);
  50. puts("to:\n");
  51. cvmx_coremask_print(&print_cm);
  52. }
  53. return 0;
  54. }
  55. /**
  56. * In CIU_FUSE for the 78XX, odd and even cores are separated out.
  57. * For example, a CIU_FUSE value of 0xfffffefffffe indicates that bits 0 and 1
  58. * are set.
  59. * This function converts the bit number in the CIU_FUSE register to a
  60. * physical core number.
  61. */
  62. static int convert_ciu_fuse_to_physical_core(int core, int max_cores)
  63. {
  64. if (!octeon_has_feature(OCTEON_FEATURE_CIU3))
  65. return core;
  66. else if (!OCTEON_IS_MODEL(OCTEON_CN78XX))
  67. return core;
  68. else if (core < (max_cores / 2))
  69. return core * 2;
  70. else
  71. return ((core - (max_cores / 2)) * 2) + 1;
  72. }
  73. /**
  74. * Get the total number of fuses blown as well as the number blown per tad.
  75. *
  76. * @param coremask fuse coremask
  77. * @param[out] tad_blown_count number of cores blown for each tad
  78. * @param num_tads number of tads
  79. * @param max_cores maximum number of cores
  80. *
  81. * @return void
  82. */
  83. void fill_tad_corecount(u64 coremask, int tad_blown_count[], int num_tads,
  84. int max_cores)
  85. {
  86. int core, physical_core;
  87. for (core = 0; core < max_cores; core++) {
  88. if (!(coremask & (1ULL << core))) {
  89. int tad;
  90. physical_core =
  91. convert_ciu_fuse_to_physical_core(core,
  92. max_cores);
  93. tad = physical_core % num_tads;
  94. tad_blown_count[tad]++;
  95. }
  96. }
  97. }
  98. u64 get_core_pattern(int num_tads, int max_cores)
  99. {
  100. u64 pattern = 1ULL;
  101. int cnt;
  102. for (cnt = 1; cnt < (max_cores / num_tads); cnt++)
  103. pattern |= pattern << num_tads;
  104. return pattern;
  105. }
  106. /**
  107. * For CN78XX and CN68XX this function returns the logical coremask from the
  108. * CIU_FUSE register value. For other models there is no difference.
  109. *
  110. * @param ciu_fuse_value fuse value from CIU_FUSE register
  111. * @return logical coremask of CIU_FUSE value.
  112. */
  113. u64 get_logical_coremask(u64 ciu_fuse_value)
  114. {
  115. int tad_blown_count[MAX_CORE_TADS] = {0};
  116. int tad;
  117. u64 logical_coremask = 0;
  118. u64 tad_mask, pattern;
  119. int num_tads, max_cores;
  120. if (OCTEON_IS_MODEL(OCTEON_CN78XX)) {
  121. num_tads = 8;
  122. max_cores = 48;
  123. } else if (OCTEON_IS_MODEL(OCTEON_CN73XX) ||
  124. OCTEON_IS_MODEL(OCTEON_CNF75XX)) {
  125. num_tads = 4;
  126. max_cores = 16;
  127. } else if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
  128. num_tads = 4;
  129. max_cores = 32;
  130. } else {
  131. /* Most Octeon devices don't need any mapping. */
  132. return ciu_fuse_value;
  133. }
  134. pattern = get_core_pattern(num_tads, max_cores);
  135. fill_tad_corecount(ciu_fuse_value, tad_blown_count,
  136. num_tads, max_cores);
  137. for (tad = 0; tad < num_tads; tad++) {
  138. tad_mask = pattern << tad;
  139. logical_coremask |= tad_mask >> (tad_blown_count[tad] * num_tads);
  140. }
  141. return logical_coremask;
  142. }
  143. /**
  144. * Returns the available coremask either from env or fuses.
  145. * If the fuses are blown and locked, they are the definitive coremask.
  146. *
  147. * @param pcm pointer to coremask to fill in
  148. * @return pointer to coremask
  149. */
  150. struct cvmx_coremask *octeon_get_available_coremask(struct cvmx_coremask *pcm)
  151. {
  152. u8 node_mask = 0x01; /* ToDo: Currently only one node is supported */
  153. u64 ciu_fuse;
  154. u64 cores;
  155. cvmx_coremask_clear_all(pcm);
  156. if (octeon_has_feature(OCTEON_FEATURE_CIU3)) {
  157. int node;
  158. cvmx_coremask_for_each_node(node, node_mask) {
  159. ciu_fuse = (csr_rd(CVMX_CIU_FUSE) &
  160. 0x0000FFFFFFFFFFFFULL);
  161. ciu_fuse = get_logical_coremask(ciu_fuse);
  162. cvmx_coremask_set64_node(pcm, node, ciu_fuse);
  163. }
  164. return pcm;
  165. }
  166. ciu_fuse = (csr_rd(CVMX_CIU_FUSE) & 0x0000FFFFFFFFFFFFULL);
  167. ciu_fuse = get_logical_coremask(ciu_fuse);
  168. if (OCTEON_IS_MODEL(OCTEON_CN68XX))
  169. cvmx_coremask_set64(pcm, ciu_fuse);
  170. /* Get number of cores from fuse register, convert to coremask */
  171. cores = __builtin_popcountll(ciu_fuse);
  172. cvmx_coremask_set_cores(pcm, 0, cores);
  173. return pcm;
  174. }
  175. int cvmx_coremask_str2bmp(struct cvmx_coremask *pcm, char *hexstr)
  176. {
  177. int i, j;
  178. int l; /* length of the hexstr in characters */
  179. int lb; /* number of bits taken by hexstr */
  180. int hldr_offset;/* holder's offset within the coremask */
  181. int hldr_xsz; /* holder's size in the number of hex digits */
  182. u64 h;
  183. char c;
  184. #define MINUS_ONE (hexstr[0] == '-' && hexstr[1] == '1' && hexstr[2] == 0)
  185. if (MINUS_ONE) {
  186. cvmx_coremask_set_all(pcm);
  187. return 0;
  188. }
  189. /* Skip '0x' from hexstr */
  190. if (hexstr[0] == '0' && (hexstr[1] == 'x' || hexstr[1] == 'X'))
  191. hexstr += 2;
  192. if (!strlen(hexstr)) {
  193. printf("%s: Error: hex string is empty\n", __func__);
  194. return -2;
  195. }
  196. /* Trim leading zeros */
  197. while (*hexstr == '0')
  198. hexstr++;
  199. cvmx_coremask_clear_all(pcm);
  200. l = strlen(hexstr);
  201. /* If length is 0 then the hex string must be all zeros */
  202. if (l == 0)
  203. return 0;
  204. for (i = 0; i < l; i++) {
  205. if (isxdigit((int)hexstr[i]) == 0) {
  206. printf("%s: Non-hex digit within hexstr\n", __func__);
  207. return -2;
  208. }
  209. }
  210. lb = (l - 1) * 4;
  211. if (hexstr[0] > '7')
  212. lb += 4;
  213. else if (hexstr[0] > '3')
  214. lb += 3;
  215. else if (hexstr[0] > '1')
  216. lb += 2;
  217. else
  218. lb += 1;
  219. if (lb > CVMX_MIPS_MAX_CORES) {
  220. printf("%s: hexstr (%s) is too long\n", __func__, hexstr);
  221. return -1;
  222. }
  223. hldr_offset = 0;
  224. hldr_xsz = 2 * sizeof(u64);
  225. for (i = l; i > 0; i -= hldr_xsz) {
  226. c = hexstr[i];
  227. hexstr[i] = 0;
  228. j = i - hldr_xsz;
  229. if (j < 0)
  230. j = 0;
  231. h = simple_strtoull(&hexstr[j], NULL, 16);
  232. if (errno == EINVAL) {
  233. printf("%s: strtou returns w/ EINVAL\n", __func__);
  234. return -2;
  235. }
  236. pcm->coremask_bitmap[hldr_offset] = h;
  237. hexstr[i] = c;
  238. hldr_offset++;
  239. }
  240. return 0;
  241. }
  242. void cvmx_coremask_print(const struct cvmx_coremask *pcm)
  243. {
  244. int i, j;
  245. int start;
  246. int found = 0;
  247. /*
  248. * Print one node per line. Since the bitmap is stored LSB to MSB
  249. * we reverse the order when printing.
  250. */
  251. if (!octeon_has_feature(OCTEON_FEATURE_MULTINODE)) {
  252. start = 0;
  253. for (j = CVMX_COREMASK_MAX_CORES_PER_NODE -
  254. CVMX_COREMASK_HLDRSZ;
  255. j >= 0; j -= CVMX_COREMASK_HLDRSZ) {
  256. if (pcm->coremask_bitmap[j / CVMX_COREMASK_HLDRSZ] != 0)
  257. start = 1;
  258. if (start) {
  259. printf(" 0x%llx",
  260. (u64)pcm->coremask_bitmap[j /
  261. CVMX_COREMASK_HLDRSZ]);
  262. }
  263. }
  264. if (start)
  265. found = 1;
  266. /*
  267. * If the coremask is empty print <EMPTY> so it is not
  268. * confusing
  269. */
  270. if (!found)
  271. printf("<EMPTY>");
  272. printf("\n");
  273. return;
  274. }
  275. for (i = 0; i < CVMX_MAX_USED_CORES_BMP;
  276. i += CVMX_COREMASK_MAX_CORES_PER_NODE) {
  277. printf("%s node %d:", i > 0 ? "\n" : "",
  278. cvmx_coremask_core_to_node(i));
  279. start = 0;
  280. for (j = i + CVMX_COREMASK_MAX_CORES_PER_NODE -
  281. CVMX_COREMASK_HLDRSZ;
  282. j >= i;
  283. j -= CVMX_COREMASK_HLDRSZ) {
  284. /* Don't start printing until we get a non-zero word. */
  285. if (pcm->coremask_bitmap[j / CVMX_COREMASK_HLDRSZ] != 0)
  286. start = 1;
  287. if (start) {
  288. printf(" 0x%llx", (u64)pcm->coremask_bitmap[j /
  289. CVMX_COREMASK_HLDRSZ]);
  290. }
  291. }
  292. if (start)
  293. found = 1;
  294. }
  295. i /= CVMX_COREMASK_HLDRSZ;
  296. for (; i < CVMX_COREMASK_BMPSZ; i++) {
  297. if (pcm->coremask_bitmap[i]) {
  298. printf(" EXTRA GARBAGE[%i]: %016llx\n", i,
  299. (u64)pcm->coremask_bitmap[i]);
  300. }
  301. }
  302. /* If the coremask is empty print <EMPTY> so it is not confusing */
  303. if (!found)
  304. printf("<EMPTY>");
  305. printf("\n");
  306. }