cpu.c 2.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2020 Marvell International Ltd.
  4. */
  5. #include <asm/global_data.h>
  6. #include <linux/bitfield.h>
  7. #include <linux/bitops.h>
  8. #include <linux/compat.h>
  9. #include <linux/io.h>
  10. #include <mach/clock.h>
  11. #include <mach/cavm-reg.h>
  12. DECLARE_GLOBAL_DATA_PTR;
  13. /*
  14. * TRUE for devices having registers with little-endian byte
  15. * order, FALSE for registers with native-endian byte order.
  16. * PCI mandates little-endian, USB and SATA are configurable,
  17. * but we chose little-endian for these.
  18. *
  19. * This table will be referened in the Octeon platform specific
  20. * mangle-port.h header.
  21. */
  22. const bool octeon_should_swizzle_table[256] = {
  23. [0x00] = true, /* bootbus/CF */
  24. [0x1b] = true, /* PCI mmio window */
  25. [0x1c] = true, /* PCI mmio window */
  26. [0x1d] = true, /* PCI mmio window */
  27. [0x1e] = true, /* PCI mmio window */
  28. [0x68] = true, /* OCTEON III USB */
  29. [0x69] = true, /* OCTEON III USB */
  30. [0x6c] = true, /* OCTEON III SATA */
  31. [0x6f] = true, /* OCTEON II USB */
  32. };
  33. static int get_clocks(void)
  34. {
  35. const u64 ref_clock = PLL_REF_CLK;
  36. void __iomem *rst_boot;
  37. u64 val;
  38. rst_boot = ioremap(CAVM_RST_BOOT, 0);
  39. val = ioread64(rst_boot);
  40. gd->cpu_clk = ref_clock * FIELD_GET(RST_BOOT_C_MUL, val);
  41. gd->bus_clk = ref_clock * FIELD_GET(RST_BOOT_PNR_MUL, val);
  42. debug("%s: cpu: %lu, bus: %lu\n", __func__, gd->cpu_clk, gd->bus_clk);
  43. return 0;
  44. }
  45. /* Early mach init code run from flash */
  46. int mach_cpu_init(void)
  47. {
  48. void __iomem *mio_boot_reg_cfg0;
  49. /* Remap boot-bus 0x1fc0.0000 -> 0x1f40.0000 */
  50. /* ToDo: Move this to an early running bus (bootbus) DM driver */
  51. mio_boot_reg_cfg0 = ioremap(CAVM_MIO_BOOT_REG_CFG0, 0);
  52. clrsetbits_be64(mio_boot_reg_cfg0, 0xffff, 0x1f40);
  53. /* Get clocks and store them in GD */
  54. get_clocks();
  55. return 0;
  56. }
  57. /**
  58. * Returns number of cores
  59. *
  60. * @return number of CPU cores for the specified node
  61. */
  62. static int cavm_octeon_num_cores(void)
  63. {
  64. void __iomem *ciu_fuse;
  65. ciu_fuse = ioremap(CAVM_CIU_FUSE, 0);
  66. return fls64(ioread64(ciu_fuse) & 0xffffffffffff);
  67. }
  68. int print_cpuinfo(void)
  69. {
  70. printf("SoC: Octeon CN73xx (%d cores)\n", cavm_octeon_num_cores());
  71. return 0;
  72. }