cache.c 481 B

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2020 Marvell International Ltd.
  4. */
  5. #include <cpu_func.h>
  6. /* Octeon memory write barrier */
  7. #define CVMX_SYNCW asm volatile ("syncw\nsyncw\n" : : : "memory")
  8. void flush_dcache_range(ulong start_addr, ulong stop)
  9. {
  10. /* Flush all pending writes */
  11. CVMX_SYNCW;
  12. }
  13. void flush_cache(ulong start_addr, ulong size)
  14. {
  15. }
  16. void invalidate_dcache_range(ulong start_addr, ulong stop)
  17. {
  18. /* Don't need to do anything for OCTEON */
  19. }