socfpga_common.h 6.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2012 Altera Corporation <www.altera.com>
  4. */
  5. #ifndef __CONFIG_SOCFPGA_COMMON_H__
  6. #define __CONFIG_SOCFPGA_COMMON_H__
  7. #include <linux/stringify.h>
  8. /*
  9. * High level configuration
  10. */
  11. #define CONFIG_CLOCKS
  12. #define CONFIG_TIMESTAMP /* Print image info with timestamp */
  13. /*
  14. * Memory configurations
  15. */
  16. #define PHYS_SDRAM_1 0x0
  17. #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
  18. #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
  19. #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
  20. #define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE
  21. #define CONFIG_SPL_PAD_TO 0x10000
  22. #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
  23. #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
  24. #define CONFIG_SPL_PAD_TO 0x40000
  25. /* SPL memory allocation configuration, this is for FAT implementation */
  26. #ifndef CONFIG_SYS_SPL_MALLOC_SIZE
  27. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000
  28. #endif
  29. #define CONFIG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \
  30. CONFIG_SYS_SPL_MALLOC_SIZE)
  31. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \
  32. CONFIG_SYS_INIT_RAM_SIZE)
  33. #endif
  34. /*
  35. * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal
  36. * SRAM as bootcounter storage. Make sure to not put the stack directly
  37. * at this address to not overwrite the bootcounter by checking, if the
  38. * bootcounter address is located in the internal SRAM.
  39. */
  40. #if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \
  41. (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \
  42. CONFIG_SYS_INIT_RAM_SIZE)))
  43. #define CONFIG_SPL_STACK CONFIG_SYS_BOOTCOUNT_ADDR
  44. #else
  45. #define CONFIG_SPL_STACK \
  46. (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
  47. #endif
  48. /*
  49. * U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc
  50. * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage
  51. * in U-Boot pre-reloc is higher than in SPL.
  52. */
  53. #if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR
  54. #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK_R_ADDR
  55. #else
  56. #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
  57. #endif
  58. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  59. /*
  60. * U-Boot general configurations
  61. */
  62. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
  63. /* Print buffer size */
  64. #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
  65. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  66. /* Boot argument buffer size */
  67. /*
  68. * Cache
  69. */
  70. #define CONFIG_SYS_L2_PL310
  71. #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
  72. /*
  73. * Ethernet on SoC (EMAC)
  74. */
  75. #ifdef CONFIG_CMD_NET
  76. #define CONFIG_DW_ALTDESCRIPTOR
  77. #endif
  78. /*
  79. * FPGA Driver
  80. */
  81. #ifdef CONFIG_CMD_FPGA
  82. #define CONFIG_FPGA_COUNT 1
  83. #endif
  84. /*
  85. * L4 OSC1 Timer 0
  86. */
  87. #ifndef CONFIG_TIMER
  88. #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
  89. #define CONFIG_SYS_TIMER_COUNTS_DOWN
  90. #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
  91. #ifndef CONFIG_SYS_TIMER_RATE
  92. #define CONFIG_SYS_TIMER_RATE 25000000
  93. #endif
  94. #endif
  95. /*
  96. * L4 Watchdog
  97. */
  98. #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
  99. #define CONFIG_DW_WDT_CLOCK_KHZ 25000
  100. /*
  101. * MMC Driver
  102. */
  103. #ifdef CONFIG_CMD_MMC
  104. /* FIXME */
  105. /* using smaller max blk cnt to avoid flooding the limited stack we have */
  106. #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
  107. #endif
  108. /*
  109. * NAND Support
  110. */
  111. #ifdef CONFIG_NAND_DENALI
  112. #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
  113. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  114. #define CONFIG_SYS_NAND_ONFI_DETECTION
  115. #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
  116. #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
  117. #endif
  118. /*
  119. * QSPI support
  120. */
  121. /* QSPI reference clock */
  122. #ifndef __ASSEMBLY__
  123. unsigned int cm_get_qspi_controller_clk_hz(void);
  124. #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
  125. #endif
  126. /*
  127. * USB
  128. */
  129. /*
  130. * USB Gadget (DFU, UMS)
  131. */
  132. #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
  133. #define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024)
  134. #define DFU_DEFAULT_POLL_TIMEOUT 300
  135. /* USB IDs */
  136. #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
  137. #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
  138. #endif
  139. /*
  140. * U-Boot environment
  141. */
  142. /* Environment for SDMMC boot */
  143. /* Environment for QSPI boot */
  144. /*
  145. * SPL
  146. *
  147. * SRAM Memory layout for gen 5:
  148. *
  149. * 0xFFFF_0000 ...... Start of SRAM
  150. * 0xFFFF_xxxx ...... Top of stack (grows down)
  151. * 0xFFFF_yyyy ...... Global Data
  152. * 0xFFFF_zzzz ...... Malloc area
  153. * 0xFFFF_FFFF ...... End of SRAM
  154. *
  155. * SRAM Memory layout for Arria 10:
  156. * 0xFFE0_0000 ...... Start of SRAM (bottom)
  157. * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
  158. * 0xFFEy_yyyy ...... Global Data
  159. * 0xFFEz_zzzz ...... Malloc area (grows up to top)
  160. * 0xFFE3_FFFF ...... End of SRAM (top)
  161. */
  162. #ifndef CONFIG_SPL_TEXT_BASE
  163. #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
  164. #endif
  165. /* SPL SDMMC boot support */
  166. #ifdef CONFIG_SPL_MMC_SUPPORT
  167. #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
  168. #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
  169. #endif
  170. #else
  171. #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
  172. #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
  173. #endif
  174. #endif
  175. /* SPL QSPI boot support */
  176. /* SPL NAND boot support */
  177. #ifdef CONFIG_SPL_NAND_SUPPORT
  178. #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
  179. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
  180. #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
  181. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x100000
  182. #endif
  183. #endif
  184. /* Extra Environment */
  185. #ifndef CONFIG_SPL_BUILD
  186. #ifdef CONFIG_CMD_DHCP
  187. #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
  188. #else
  189. #define BOOT_TARGET_DEVICES_DHCP(func)
  190. #endif
  191. #if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
  192. #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
  193. #else
  194. #define BOOT_TARGET_DEVICES_PXE(func)
  195. #endif
  196. #ifdef CONFIG_CMD_MMC
  197. #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
  198. #else
  199. #define BOOT_TARGET_DEVICES_MMC(func)
  200. #endif
  201. #define BOOT_TARGET_DEVICES(func) \
  202. BOOT_TARGET_DEVICES_MMC(func) \
  203. BOOT_TARGET_DEVICES_PXE(func) \
  204. BOOT_TARGET_DEVICES_DHCP(func)
  205. #include <config_distro_bootcmd.h>
  206. #ifndef CONFIG_EXTRA_ENV_SETTINGS
  207. #define CONFIG_EXTRA_ENV_SETTINGS \
  208. "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
  209. "bootm_size=0xa000000\0" \
  210. "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
  211. "fdt_addr_r=0x02000000\0" \
  212. "scriptaddr=0x02100000\0" \
  213. "pxefile_addr_r=0x02200000\0" \
  214. "ramdisk_addr_r=0x02300000\0" \
  215. "socfpga_legacy_reset_compat=1\0" \
  216. BOOTENV
  217. #endif
  218. #endif
  219. #endif /* __CONFIG_SOCFPGA_COMMON_H__ */