zynqmp-sm-k26-revA.dts 7.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * dts file for Xilinx ZynqMP SM-K26 rev1/B/A
  4. *
  5. * (C) Copyright 2020 - 2021, Xilinx, Inc.
  6. *
  7. * Michal Simek <michal.simek@xilinx.com>
  8. */
  9. /dts-v1/;
  10. #include "zynqmp.dtsi"
  11. #include "zynqmp-clk-ccf.dtsi"
  12. #include <dt-bindings/input/input.h>
  13. #include <dt-bindings/gpio/gpio.h>
  14. #include <dt-bindings/phy/phy.h>
  15. / {
  16. model = "ZynqMP SM-K26 Rev1/B/A";
  17. compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB",
  18. "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26",
  19. "xlnx,zynqmp";
  20. aliases {
  21. i2c0 = &i2c0;
  22. i2c1 = &i2c1;
  23. mmc0 = &sdhci0;
  24. mmc1 = &sdhci1;
  25. nvmem0 = &eeprom;
  26. nvmem1 = &eeprom_cc;
  27. rtc0 = &rtc;
  28. serial0 = &uart0;
  29. serial1 = &uart1;
  30. serial2 = &dcc;
  31. spi0 = &qspi;
  32. spi1 = &spi0;
  33. spi2 = &spi1;
  34. usb0 = &usb0;
  35. usb1 = &usb1;
  36. };
  37. chosen {
  38. bootargs = "earlycon";
  39. stdout-path = "serial1:115200n8";
  40. };
  41. memory@0 {
  42. device_type = "memory"; /* 4GB */
  43. reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  44. };
  45. gpio-keys {
  46. compatible = "gpio-keys";
  47. autorepeat;
  48. fwuen {
  49. label = "fwuen";
  50. gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
  51. };
  52. };
  53. leds {
  54. compatible = "gpio-leds";
  55. ds35-led {
  56. label = "heartbeat";
  57. gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
  58. linux,default-trigger = "heartbeat";
  59. };
  60. ds36-led {
  61. label = "vbus_det";
  62. gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
  63. default-state = "on";
  64. };
  65. };
  66. ams {
  67. compatible = "iio-hwmon";
  68. io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
  69. <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,
  70. <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,
  71. <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,
  72. <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,
  73. <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,
  74. <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,
  75. <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,
  76. <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,
  77. <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;
  78. };
  79. };
  80. &uart1 { /* MIO36/MIO37 */
  81. status = "okay";
  82. };
  83. &qspi { /* MIO 0-5 - U143 */
  84. status = "okay";
  85. flash@0 { /* MT25QU512A */
  86. compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */
  87. #address-cells = <1>;
  88. #size-cells = <1>;
  89. reg = <0>;
  90. spi-tx-bus-width = <1>;
  91. spi-rx-bus-width = <4>;
  92. spi-max-frequency = <40000000>; /* 40MHz */
  93. partition@0 {
  94. label = "Image Selector";
  95. reg = <0x0 0x80000>; /* 512KB */
  96. read-only;
  97. lock;
  98. };
  99. partition@80000 {
  100. label = "Image Selector Golden";
  101. reg = <0x80000 0x80000>; /* 512KB */
  102. read-only;
  103. lock;
  104. };
  105. partition@100000 {
  106. label = "Persistent Register";
  107. reg = <0x100000 0x20000>; /* 128KB */
  108. };
  109. partition@120000 {
  110. label = "Persistent Register Backup";
  111. reg = <0x120000 0x20000>; /* 128KB */
  112. };
  113. partition@140000 {
  114. label = "Open_1";
  115. reg = <0x140000 0xC0000>; /* 768KB */
  116. };
  117. partition@200000 {
  118. label = "Image A (FSBL, PMU, ATF, U-Boot)";
  119. reg = <0x200000 0xD00000>; /* 13MB */
  120. };
  121. partition@f00000 {
  122. label = "ImgSel Image A Catch";
  123. reg = <0xF00000 0x80000>; /* 512KB */
  124. read-only;
  125. lock;
  126. };
  127. partition@f80000 {
  128. label = "Image B (FSBL, PMU, ATF, U-Boot)";
  129. reg = <0xF80000 0xD00000>; /* 13MB */
  130. };
  131. partition@1c80000 {
  132. label = "ImgSel Image B Catch";
  133. reg = <0x1C80000 0x80000>; /* 512KB */
  134. read-only;
  135. lock;
  136. };
  137. partition@1d00000 {
  138. label = "Open_2";
  139. reg = <0x1D00000 0x100000>; /* 1MB */
  140. };
  141. partition@1e00000 {
  142. label = "Recovery Image";
  143. reg = <0x1E00000 0x200000>; /* 2MB */
  144. read-only;
  145. lock;
  146. };
  147. partition@2000000 {
  148. label = "Recovery Image Backup";
  149. reg = <0x2000000 0x200000>; /* 2MB */
  150. read-only;
  151. lock;
  152. };
  153. partition@2200000 {
  154. label = "U-Boot storage variables";
  155. reg = <0x2200000 0x20000>; /* 128KB */
  156. };
  157. partition@2220000 {
  158. label = "U-Boot storage variables backup";
  159. reg = <0x2220000 0x20000>; /* 128KB */
  160. };
  161. partition@2240000 {
  162. label = "SHA256";
  163. reg = <0x2240000 0x10000>; /* 256B but 64KB sector */
  164. read-only;
  165. lock;
  166. };
  167. partition@2250000 {
  168. label = "User";
  169. reg = <0x2250000 0x1db0000>; /* 29.5 MB */
  170. };
  171. };
  172. };
  173. &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A */
  174. status = "okay";
  175. non-removable;
  176. disable-wp;
  177. bus-width = <8>;
  178. xlnx,mio-bank = <0>;
  179. };
  180. &spi1 { /* MIO6, 9-11 */
  181. status = "okay";
  182. label = "TPM";
  183. num-cs = <1>;
  184. tpm@0 { /* slm9670 - U144 */
  185. compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
  186. reg = <0>;
  187. spi-max-frequency = <18500000>;
  188. };
  189. };
  190. &i2c1 {
  191. status = "okay";
  192. u-boot,dm-pre-reloc;
  193. clock-frequency = <400000>;
  194. scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
  195. sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
  196. eeprom: eeprom@50 { /* u46 - also at address 0x58 */
  197. u-boot,dm-pre-reloc;
  198. compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
  199. reg = <0x50>;
  200. /* WP pin EE_WP_EN connected to slg7x644092@68 */
  201. };
  202. eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */
  203. u-boot,dm-pre-reloc;
  204. compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
  205. reg = <0x51>;
  206. };
  207. /* da9062@30 - u170 - also at address 0x31 */
  208. /* da9131@33 - u167 */
  209. da9131: pmic@33 {
  210. compatible = "dlg,da9131";
  211. reg = <0x33>;
  212. regulators {
  213. da9131_buck1: buck1 {
  214. regulator-name = "da9131_buck1";
  215. regulator-boot-on;
  216. regulator-always-on;
  217. };
  218. da9131_buck2: buck2 {
  219. regulator-name = "da9131_buck2";
  220. regulator-boot-on;
  221. regulator-always-on;
  222. };
  223. };
  224. };
  225. /* da9130@32 - u166 */
  226. da9130: pmic@32 {
  227. compatible = "dlg,da9130";
  228. reg = <0x32>;
  229. regulators {
  230. da9130_buck1: buck1 {
  231. regulator-name = "da9130_buck1";
  232. regulator-boot-on;
  233. regulator-always-on;
  234. };
  235. };
  236. };
  237. /* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */
  238. /*
  239. * stdp4320 - u27 FW has below two issues to be fixed in next board revision.
  240. * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.
  241. * Address conflict with slg7x644091@70 making both the devices NOT accessible.
  242. * With the FW fix, stdp4320 should respond to address 0x73 only.
  243. */
  244. /* slg7x644092@68 - u169 */
  245. /* Also connected via JA1C as C23/C24 */
  246. };
  247. &gpio {
  248. status = "okay";
  249. gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
  250. "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */
  251. "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
  252. "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
  253. "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */
  254. "I2C1_SDA", "", "", "", "", /* 25 - 29 */
  255. "", "", "", "", "", /* 30 - 34 */
  256. "", "", "", "", "", /* 35 - 39 */
  257. "", "", "", "", "", /* 40 - 44 */
  258. "", "", "", "", "", /* 45 - 49 */
  259. "", "", "", "", "", /* 50 - 54 */
  260. "", "", "", "", "", /* 55 - 59 */
  261. "", "", "", "", "", /* 60 - 64 */
  262. "", "", "", "", "", /* 65 - 69 */
  263. "", "", "", "", "", /* 70 - 74 */
  264. "", "", "", /* 75 - 77, MIO end and EMIO start */
  265. "", "", /* 78 - 79 */
  266. "", "", "", "", "", /* 80 - 84 */
  267. "", "", "", "", "", /* 85 - 89 */
  268. "", "", "", "", "", /* 90 - 94 */
  269. "", "", "", "", "", /* 95 - 99 */
  270. "", "", "", "", "", /* 100 - 104 */
  271. "", "", "", "", "", /* 105 - 109 */
  272. "", "", "", "", "", /* 110 - 114 */
  273. "", "", "", "", "", /* 115 - 119 */
  274. "", "", "", "", "", /* 120 - 124 */
  275. "", "", "", "", "", /* 125 - 129 */
  276. "", "", "", "", "", /* 130 - 134 */
  277. "", "", "", "", "", /* 135 - 139 */
  278. "", "", "", "", "", /* 140 - 144 */
  279. "", "", "", "", "", /* 145 - 149 */
  280. "", "", "", "", "", /* 150 - 154 */
  281. "", "", "", "", "", /* 155 - 159 */
  282. "", "", "", "", "", /* 160 - 164 */
  283. "", "", "", "", "", /* 165 - 169 */
  284. "", "", "", ""; /* 170 - 174 */
  285. };
  286. &xilinx_ams {
  287. status = "okay";
  288. };
  289. &ams_ps {
  290. status = "okay";
  291. };
  292. &ams_pl {
  293. status = "okay";
  294. };