display.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Google Inc.
  4. *
  5. * Extracted from Chromium coreboot commit 3f59b13d
  6. */
  7. #include <common.h>
  8. #include <bootstage.h>
  9. #include <dm.h>
  10. #include <edid.h>
  11. #include <errno.h>
  12. #include <display.h>
  13. #include <edid.h>
  14. #include <lcd.h>
  15. #include <part.h>
  16. #include <video.h>
  17. #include <asm/gpio.h>
  18. #include <asm/io.h>
  19. #include <asm/arch/clock.h>
  20. #include <asm/arch/pwm.h>
  21. #include <asm/arch-tegra/dc.h>
  22. #include <dm/uclass-internal.h>
  23. #include "displayport.h"
  24. /* return in 1000ths of a Hertz */
  25. static int tegra_dc_calc_refresh(const struct display_timing *timing)
  26. {
  27. int h_total, v_total, refresh;
  28. int pclk = timing->pixelclock.typ;
  29. h_total = timing->hactive.typ + timing->hfront_porch.typ +
  30. timing->hback_porch.typ + timing->hsync_len.typ;
  31. v_total = timing->vactive.typ + timing->vfront_porch.typ +
  32. timing->vback_porch.typ + timing->vsync_len.typ;
  33. if (!pclk || !h_total || !v_total)
  34. return 0;
  35. refresh = pclk / h_total;
  36. refresh *= 1000;
  37. refresh /= v_total;
  38. return refresh;
  39. }
  40. static void print_mode(const struct display_timing *timing)
  41. {
  42. int refresh = tegra_dc_calc_refresh(timing);
  43. debug("MODE:%dx%d@%d.%03uHz pclk=%d\n",
  44. timing->hactive.typ, timing->vactive.typ, refresh / 1000,
  45. refresh % 1000, timing->pixelclock.typ);
  46. }
  47. static int update_display_mode(struct dc_ctlr *disp_ctrl,
  48. const struct display_timing *timing,
  49. int href_to_sync, int vref_to_sync)
  50. {
  51. print_mode(timing);
  52. writel(0x1, &disp_ctrl->disp.disp_timing_opt);
  53. writel(vref_to_sync << 16 | href_to_sync,
  54. &disp_ctrl->disp.ref_to_sync);
  55. writel(timing->vsync_len.typ << 16 | timing->hsync_len.typ,
  56. &disp_ctrl->disp.sync_width);
  57. writel(((timing->vback_porch.typ - vref_to_sync) << 16) |
  58. timing->hback_porch.typ, &disp_ctrl->disp.back_porch);
  59. writel(((timing->vfront_porch.typ + vref_to_sync) << 16) |
  60. timing->hfront_porch.typ, &disp_ctrl->disp.front_porch);
  61. writel(timing->hactive.typ | (timing->vactive.typ << 16),
  62. &disp_ctrl->disp.disp_active);
  63. /**
  64. * We want to use PLLD_out0, which is PLLD / 2:
  65. * PixelClock = (PLLD / 2) / ShiftClockDiv / PixelClockDiv.
  66. *
  67. * Currently most panels work inside clock range 50MHz~100MHz, and PLLD
  68. * has some requirements to have VCO in range 500MHz~1000MHz (see
  69. * clock.c for more detail). To simplify calculation, we set
  70. * PixelClockDiv to 1 and ShiftClockDiv to 1. In future these values
  71. * may be calculated by clock_display, to allow wider frequency range.
  72. *
  73. * Note ShiftClockDiv is a 7.1 format value.
  74. */
  75. const u32 shift_clock_div = 1;
  76. writel((PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT) |
  77. ((shift_clock_div - 1) * 2) << SHIFT_CLK_DIVIDER_SHIFT,
  78. &disp_ctrl->disp.disp_clk_ctrl);
  79. debug("%s: PixelClock=%u, ShiftClockDiv=%u\n", __func__,
  80. timing->pixelclock.typ, shift_clock_div);
  81. return 0;
  82. }
  83. static u32 tegra_dc_poll_register(void *reg,
  84. u32 mask, u32 exp_val, u32 poll_interval_us, u32 timeout_us)
  85. {
  86. u32 temp = timeout_us;
  87. u32 reg_val = 0;
  88. do {
  89. udelay(poll_interval_us);
  90. reg_val = readl(reg);
  91. if (timeout_us > poll_interval_us)
  92. timeout_us -= poll_interval_us;
  93. else
  94. break;
  95. } while ((reg_val & mask) != exp_val);
  96. if ((reg_val & mask) == exp_val)
  97. return 0; /* success */
  98. return temp;
  99. }
  100. int tegra_dc_sor_general_act(struct dc_ctlr *disp_ctrl)
  101. {
  102. writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
  103. if (tegra_dc_poll_register(&disp_ctrl->cmd.state_ctrl,
  104. GENERAL_ACT_REQ, 0, 100,
  105. DC_POLL_TIMEOUT_MS * 1000)) {
  106. debug("dc timeout waiting for DC to stop\n");
  107. return -ETIMEDOUT;
  108. }
  109. return 0;
  110. }
  111. static struct display_timing min_mode = {
  112. .hsync_len = { .typ = 1 },
  113. .vsync_len = { .typ = 1 },
  114. .hback_porch = { .typ = 20 },
  115. .vback_porch = { .typ = 0 },
  116. .hactive = { .typ = 16 },
  117. .vactive = { .typ = 16 },
  118. .hfront_porch = { .typ = 1 },
  119. .vfront_porch = { .typ = 2 },
  120. };
  121. /* Disable windows and set minimum raster timings */
  122. void tegra_dc_sor_disable_win_short_raster(struct dc_ctlr *disp_ctrl,
  123. int *dc_reg_ctx)
  124. {
  125. const int href_to_sync = 0, vref_to_sync = 1;
  126. int selected_windows, i;
  127. selected_windows = readl(&disp_ctrl->cmd.disp_win_header);
  128. /* Store and clear window options */
  129. for (i = 0; i < DC_N_WINDOWS; ++i) {
  130. writel(WINDOW_A_SELECT << i, &disp_ctrl->cmd.disp_win_header);
  131. dc_reg_ctx[i] = readl(&disp_ctrl->win.win_opt);
  132. writel(0, &disp_ctrl->win.win_opt);
  133. writel(WIN_A_ACT_REQ << i, &disp_ctrl->cmd.state_ctrl);
  134. }
  135. writel(selected_windows, &disp_ctrl->cmd.disp_win_header);
  136. /* Store current raster timings and set minimum timings */
  137. dc_reg_ctx[i++] = readl(&disp_ctrl->disp.ref_to_sync);
  138. writel(href_to_sync | (vref_to_sync << 16),
  139. &disp_ctrl->disp.ref_to_sync);
  140. dc_reg_ctx[i++] = readl(&disp_ctrl->disp.sync_width);
  141. writel(min_mode.hsync_len.typ | (min_mode.vsync_len.typ << 16),
  142. &disp_ctrl->disp.sync_width);
  143. dc_reg_ctx[i++] = readl(&disp_ctrl->disp.back_porch);
  144. writel(min_mode.hback_porch.typ | (min_mode.vback_porch.typ << 16),
  145. &disp_ctrl->disp.back_porch);
  146. dc_reg_ctx[i++] = readl(&disp_ctrl->disp.front_porch);
  147. writel(min_mode.hfront_porch.typ | (min_mode.vfront_porch.typ << 16),
  148. &disp_ctrl->disp.front_porch);
  149. dc_reg_ctx[i++] = readl(&disp_ctrl->disp.disp_active);
  150. writel(min_mode.hactive.typ | (min_mode.vactive.typ << 16),
  151. &disp_ctrl->disp.disp_active);
  152. writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
  153. }
  154. /* Restore previous windows status and raster timings */
  155. void tegra_dc_sor_restore_win_and_raster(struct dc_ctlr *disp_ctrl,
  156. int *dc_reg_ctx)
  157. {
  158. int selected_windows, i;
  159. selected_windows = readl(&disp_ctrl->cmd.disp_win_header);
  160. for (i = 0; i < DC_N_WINDOWS; ++i) {
  161. writel(WINDOW_A_SELECT << i, &disp_ctrl->cmd.disp_win_header);
  162. writel(dc_reg_ctx[i], &disp_ctrl->win.win_opt);
  163. writel(WIN_A_ACT_REQ << i, &disp_ctrl->cmd.state_ctrl);
  164. }
  165. writel(selected_windows, &disp_ctrl->cmd.disp_win_header);
  166. writel(dc_reg_ctx[i++], &disp_ctrl->disp.ref_to_sync);
  167. writel(dc_reg_ctx[i++], &disp_ctrl->disp.sync_width);
  168. writel(dc_reg_ctx[i++], &disp_ctrl->disp.back_porch);
  169. writel(dc_reg_ctx[i++], &disp_ctrl->disp.front_porch);
  170. writel(dc_reg_ctx[i++], &disp_ctrl->disp.disp_active);
  171. writel(GENERAL_UPDATE, &disp_ctrl->cmd.state_ctrl);
  172. }
  173. static int tegra_depth_for_bpp(int bpp)
  174. {
  175. switch (bpp) {
  176. case 32:
  177. return COLOR_DEPTH_R8G8B8A8;
  178. case 16:
  179. return COLOR_DEPTH_B5G6R5;
  180. default:
  181. debug("Unsupported LCD bit depth");
  182. return -1;
  183. }
  184. }
  185. static int update_window(struct dc_ctlr *disp_ctrl,
  186. u32 frame_buffer, int fb_bits_per_pixel,
  187. const struct display_timing *timing)
  188. {
  189. const u32 colour_white = 0xffffff;
  190. int colour_depth;
  191. u32 val;
  192. writel(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header);
  193. writel(((timing->vactive.typ << 16) | timing->hactive.typ),
  194. &disp_ctrl->win.size);
  195. writel(((timing->vactive.typ << 16) |
  196. (timing->hactive.typ * fb_bits_per_pixel / 8)),
  197. &disp_ctrl->win.prescaled_size);
  198. writel(((timing->hactive.typ * fb_bits_per_pixel / 8 + 31) /
  199. 32 * 32), &disp_ctrl->win.line_stride);
  200. colour_depth = tegra_depth_for_bpp(fb_bits_per_pixel);
  201. if (colour_depth == -1)
  202. return -EINVAL;
  203. writel(colour_depth, &disp_ctrl->win.color_depth);
  204. writel(frame_buffer, &disp_ctrl->winbuf.start_addr);
  205. writel(0x1000 << V_DDA_INC_SHIFT | 0x1000 << H_DDA_INC_SHIFT,
  206. &disp_ctrl->win.dda_increment);
  207. writel(colour_white, &disp_ctrl->disp.blend_background_color);
  208. writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT,
  209. &disp_ctrl->cmd.disp_cmd);
  210. writel(WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);
  211. val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
  212. val |= GENERAL_UPDATE | WIN_A_UPDATE;
  213. writel(val, &disp_ctrl->cmd.state_ctrl);
  214. /* Enable win_a */
  215. val = readl(&disp_ctrl->win.win_opt);
  216. writel(val | WIN_ENABLE, &disp_ctrl->win.win_opt);
  217. return 0;
  218. }
  219. static int tegra_dc_init(struct dc_ctlr *disp_ctrl)
  220. {
  221. /* do not accept interrupts during initialization */
  222. writel(0x00000000, &disp_ctrl->cmd.int_mask);
  223. writel(WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY,
  224. &disp_ctrl->cmd.state_access);
  225. writel(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header);
  226. writel(0x00000000, &disp_ctrl->win.win_opt);
  227. writel(0x00000000, &disp_ctrl->win.byte_swap);
  228. writel(0x00000000, &disp_ctrl->win.buffer_ctrl);
  229. writel(0x00000000, &disp_ctrl->win.pos);
  230. writel(0x00000000, &disp_ctrl->win.h_initial_dda);
  231. writel(0x00000000, &disp_ctrl->win.v_initial_dda);
  232. writel(0x00000000, &disp_ctrl->win.dda_increment);
  233. writel(0x00000000, &disp_ctrl->win.dv_ctrl);
  234. writel(0x01000000, &disp_ctrl->win.blend_layer_ctrl);
  235. writel(0x00000000, &disp_ctrl->win.blend_match_select);
  236. writel(0x00000000, &disp_ctrl->win.blend_nomatch_select);
  237. writel(0x00000000, &disp_ctrl->win.blend_alpha_1bit);
  238. writel(0x00000000, &disp_ctrl->winbuf.start_addr_hi);
  239. writel(0x00000000, &disp_ctrl->winbuf.addr_h_offset);
  240. writel(0x00000000, &disp_ctrl->winbuf.addr_v_offset);
  241. writel(0x00000000, &disp_ctrl->com.crc_checksum);
  242. writel(0x00000000, &disp_ctrl->com.pin_output_enb[0]);
  243. writel(0x00000000, &disp_ctrl->com.pin_output_enb[1]);
  244. writel(0x00000000, &disp_ctrl->com.pin_output_enb[2]);
  245. writel(0x00000000, &disp_ctrl->com.pin_output_enb[3]);
  246. writel(0x00000000, &disp_ctrl->disp.disp_signal_opt0);
  247. return 0;
  248. }
  249. static void dump_config(int panel_bpp, struct display_timing *timing)
  250. {
  251. printf("timing->hactive.typ = %d\n", timing->hactive.typ);
  252. printf("timing->vactive.typ = %d\n", timing->vactive.typ);
  253. printf("timing->pixelclock.typ = %d\n", timing->pixelclock.typ);
  254. printf("timing->hfront_porch.typ = %d\n", timing->hfront_porch.typ);
  255. printf("timing->hsync_len.typ = %d\n", timing->hsync_len.typ);
  256. printf("timing->hback_porch.typ = %d\n", timing->hback_porch.typ);
  257. printf("timing->vfront_porch.typ %d\n", timing->vfront_porch.typ);
  258. printf("timing->vsync_len.typ = %d\n", timing->vsync_len.typ);
  259. printf("timing->vback_porch.typ = %d\n", timing->vback_porch.typ);
  260. printf("panel_bits_per_pixel = %d\n", panel_bpp);
  261. }
  262. static int display_update_config_from_edid(struct udevice *dp_dev,
  263. int *panel_bppp,
  264. struct display_timing *timing)
  265. {
  266. return display_read_timing(dp_dev, timing);
  267. }
  268. static int display_init(struct udevice *dev, void *lcdbase,
  269. int fb_bits_per_pixel, struct display_timing *timing)
  270. {
  271. struct display_plat *disp_uc_plat;
  272. struct dc_ctlr *dc_ctlr;
  273. struct udevice *dp_dev;
  274. const int href_to_sync = 1, vref_to_sync = 1;
  275. int panel_bpp = 18; /* default 18 bits per pixel */
  276. u32 plld_rate;
  277. int ret;
  278. /*
  279. * Before we probe the display device (eDP), tell it that this device
  280. * is the source of the display data.
  281. */
  282. ret = uclass_find_first_device(UCLASS_DISPLAY, &dp_dev);
  283. if (ret) {
  284. debug("%s: device '%s' display not found (ret=%d)\n", __func__,
  285. dev->name, ret);
  286. return ret;
  287. }
  288. disp_uc_plat = dev_get_uclass_platdata(dp_dev);
  289. debug("Found device '%s', disp_uc_priv=%p\n", dp_dev->name,
  290. disp_uc_plat);
  291. disp_uc_plat->src_dev = dev;
  292. ret = uclass_get_device(UCLASS_DISPLAY, 0, &dp_dev);
  293. if (ret) {
  294. debug("%s: Failed to probe eDP, ret=%d\n", __func__, ret);
  295. return ret;
  296. }
  297. dc_ctlr = (struct dc_ctlr *)dev_read_addr(dev);
  298. if (ofnode_decode_display_timing(dev_ofnode(dev), 0, timing)) {
  299. debug("%s: Failed to decode display timing\n", __func__);
  300. return -EINVAL;
  301. }
  302. ret = display_update_config_from_edid(dp_dev, &panel_bpp, timing);
  303. if (ret) {
  304. debug("%s: Failed to decode EDID, using defaults\n", __func__);
  305. dump_config(panel_bpp, timing);
  306. }
  307. /*
  308. * The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER
  309. * and PIXEL_CLK_DIVIDER are zero (divide by 1). See the
  310. * update_display_mode() for detail.
  311. */
  312. plld_rate = clock_set_display_rate(timing->pixelclock.typ * 2);
  313. if (plld_rate == 0) {
  314. printf("dc: clock init failed\n");
  315. return -EIO;
  316. } else if (plld_rate != timing->pixelclock.typ * 2) {
  317. debug("dc: plld rounded to %u\n", plld_rate);
  318. timing->pixelclock.typ = plld_rate / 2;
  319. }
  320. /* Init dc */
  321. ret = tegra_dc_init(dc_ctlr);
  322. if (ret) {
  323. debug("dc: init failed\n");
  324. return ret;
  325. }
  326. /* Configure dc mode */
  327. ret = update_display_mode(dc_ctlr, timing, href_to_sync, vref_to_sync);
  328. if (ret) {
  329. debug("dc: failed to configure display mode\n");
  330. return ret;
  331. }
  332. /* Enable dp */
  333. ret = display_enable(dp_dev, panel_bpp, timing);
  334. if (ret) {
  335. debug("dc: failed to enable display: ret=%d\n", ret);
  336. return ret;
  337. }
  338. ret = update_window(dc_ctlr, (ulong)lcdbase, fb_bits_per_pixel, timing);
  339. if (ret) {
  340. debug("dc: failed to update window\n");
  341. return ret;
  342. }
  343. debug("%s: ready\n", __func__);
  344. return 0;
  345. }
  346. enum {
  347. /* Maximum LCD size we support */
  348. LCD_MAX_WIDTH = 1920,
  349. LCD_MAX_HEIGHT = 1200,
  350. LCD_MAX_LOG2_BPP = 4, /* 2^4 = 16 bpp */
  351. };
  352. static int tegra124_lcd_init(struct udevice *dev, void *lcdbase,
  353. enum video_log2_bpp l2bpp)
  354. {
  355. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  356. struct display_timing timing;
  357. int ret;
  358. clock_set_up_plldp();
  359. clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH, 408000000);
  360. clock_enable(PERIPH_ID_HOST1X);
  361. clock_enable(PERIPH_ID_DISP1);
  362. clock_enable(PERIPH_ID_PWM);
  363. clock_enable(PERIPH_ID_DPAUX);
  364. clock_enable(PERIPH_ID_SOR0);
  365. udelay(2);
  366. reset_set_enable(PERIPH_ID_HOST1X, 0);
  367. reset_set_enable(PERIPH_ID_DISP1, 0);
  368. reset_set_enable(PERIPH_ID_PWM, 0);
  369. reset_set_enable(PERIPH_ID_DPAUX, 0);
  370. reset_set_enable(PERIPH_ID_SOR0, 0);
  371. ret = display_init(dev, lcdbase, 1 << l2bpp, &timing);
  372. if (ret)
  373. return ret;
  374. uc_priv->xsize = roundup(timing.hactive.typ, 16);
  375. uc_priv->ysize = timing.vactive.typ;
  376. uc_priv->bpix = l2bpp;
  377. video_set_flush_dcache(dev, 1);
  378. debug("%s: done\n", __func__);
  379. return 0;
  380. }
  381. static int tegra124_lcd_probe(struct udevice *dev)
  382. {
  383. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  384. ulong start;
  385. int ret;
  386. start = get_timer(0);
  387. bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "lcd");
  388. ret = tegra124_lcd_init(dev, (void *)plat->base, VIDEO_BPP16);
  389. bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
  390. debug("LCD init took %lu ms\n", get_timer(start));
  391. if (ret)
  392. printf("%s: Error %d\n", __func__, ret);
  393. return 0;
  394. }
  395. static int tegra124_lcd_bind(struct udevice *dev)
  396. {
  397. struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
  398. uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
  399. (1 << VIDEO_BPP16) / 8;
  400. debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
  401. return 0;
  402. }
  403. static const struct udevice_id tegra124_lcd_ids[] = {
  404. { .compatible = "nvidia,tegra124-dc" },
  405. { }
  406. };
  407. U_BOOT_DRIVER(tegra124_dc) = {
  408. .name = "tegra124-dc",
  409. .id = UCLASS_VIDEO,
  410. .of_match = tegra124_lcd_ids,
  411. .bind = tegra124_lcd_bind,
  412. .probe = tegra124_lcd_probe,
  413. };