broadwell_igd.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * From coreboot src/soc/intel/broadwell/igd.c
  4. *
  5. * Copyright (C) 2016 Google, Inc
  6. */
  7. #include <common.h>
  8. #include <bios_emul.h>
  9. #include <bootstage.h>
  10. #include <dm.h>
  11. #include <init.h>
  12. #include <vbe.h>
  13. #include <video.h>
  14. #include <asm/cpu.h>
  15. #include <asm/intel_regs.h>
  16. #include <asm/io.h>
  17. #include <asm/mtrr.h>
  18. #include <asm/arch/cpu.h>
  19. #include <asm/arch/iomap.h>
  20. #include <asm/arch/pch.h>
  21. #include "i915_reg.h"
  22. struct broadwell_igd_priv {
  23. u8 *regs;
  24. };
  25. struct broadwell_igd_plat {
  26. u32 dp_hotplug[3];
  27. int port_select;
  28. int power_up_delay;
  29. int power_backlight_on_delay;
  30. int power_down_delay;
  31. int power_backlight_off_delay;
  32. int power_cycle_delay;
  33. int cpu_backlight;
  34. int pch_backlight;
  35. int cdclk;
  36. int pre_graphics_delay;
  37. };
  38. #define GT_RETRY 1000
  39. #define GT_CDCLK_337 0
  40. #define GT_CDCLK_450 1
  41. #define GT_CDCLK_540 2
  42. #define GT_CDCLK_675 3
  43. u32 board_map_oprom_vendev(u32 vendev)
  44. {
  45. return SA_IGD_OPROM_VENDEV;
  46. }
  47. static int poll32(u8 *addr, uint mask, uint value)
  48. {
  49. ulong start;
  50. start = get_timer(0);
  51. debug("%s: addr %p = %x\n", __func__, addr, readl(addr));
  52. while ((readl(addr) & mask) != value) {
  53. if (get_timer(start) > GT_RETRY) {
  54. debug("poll32: timeout: %x\n", readl(addr));
  55. return -ETIMEDOUT;
  56. }
  57. }
  58. return 0;
  59. }
  60. static int haswell_early_init(struct udevice *dev)
  61. {
  62. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  63. u8 *regs = priv->regs;
  64. int ret;
  65. /* Enable Force Wake */
  66. writel(0x00000020, regs + 0xa180);
  67. writel(0x00010001, regs + 0xa188);
  68. ret = poll32(regs + 0x130044, 1, 1);
  69. if (ret)
  70. goto err;
  71. /* Enable Counters */
  72. setbits_le32(regs + 0xa248, 0x00000016);
  73. /* GFXPAUSE settings */
  74. writel(0x00070020, regs + 0xa000);
  75. /* ECO Settings */
  76. clrsetbits_le32(regs + 0xa180, ~0xff3fffff, 0x15000000);
  77. /* Enable DOP Clock Gating */
  78. writel(0x000003fd, regs + 0x9424);
  79. /* Enable Unit Level Clock Gating */
  80. writel(0x00000080, regs + 0x9400);
  81. writel(0x40401000, regs + 0x9404);
  82. writel(0x00000000, regs + 0x9408);
  83. writel(0x02000001, regs + 0x940c);
  84. /*
  85. * RC6 Settings
  86. */
  87. /* Wake Rate Limits */
  88. setbits_le32(regs + 0xa090, 0x00000000);
  89. setbits_le32(regs + 0xa098, 0x03e80000);
  90. setbits_le32(regs + 0xa09c, 0x00280000);
  91. setbits_le32(regs + 0xa0a8, 0x0001e848);
  92. setbits_le32(regs + 0xa0ac, 0x00000019);
  93. /* Render/Video/Blitter Idle Max Count */
  94. writel(0x0000000a, regs + 0x02054);
  95. writel(0x0000000a, regs + 0x12054);
  96. writel(0x0000000a, regs + 0x22054);
  97. writel(0x0000000a, regs + 0x1a054);
  98. /* RC Sleep / RCx Thresholds */
  99. setbits_le32(regs + 0xa0b0, 0x00000000);
  100. setbits_le32(regs + 0xa0b4, 0x000003e8);
  101. setbits_le32(regs + 0xa0b8, 0x0000c350);
  102. /* RP Settings */
  103. setbits_le32(regs + 0xa010, 0x000f4240);
  104. setbits_le32(regs + 0xa014, 0x12060000);
  105. setbits_le32(regs + 0xa02c, 0x0000e808);
  106. setbits_le32(regs + 0xa030, 0x0003bd08);
  107. setbits_le32(regs + 0xa068, 0x000101d0);
  108. setbits_le32(regs + 0xa06c, 0x00055730);
  109. setbits_le32(regs + 0xa070, 0x0000000a);
  110. /* RP Control */
  111. writel(0x00000b92, regs + 0xa024);
  112. /* HW RC6 Control */
  113. writel(0x88040000, regs + 0xa090);
  114. /* Video Frequency Request */
  115. writel(0x08000000, regs + 0xa00c);
  116. /* Set RC6 VIDs */
  117. ret = poll32(regs + 0x138124, (1 << 31), 0);
  118. if (ret)
  119. goto err;
  120. writel(0, regs + 0x138128);
  121. writel(0x80000004, regs + 0x138124);
  122. ret = poll32(regs + 0x138124, (1 << 31), 0);
  123. if (ret)
  124. goto err;
  125. /* Enable PM Interrupts */
  126. writel(0x03000076, regs + 0x4402c);
  127. /* Enable RC6 in idle */
  128. writel(0x00040000, regs + 0xa094);
  129. return 0;
  130. err:
  131. debug("%s: ret=%d\n", __func__, ret);
  132. return ret;
  133. };
  134. static int haswell_late_init(struct udevice *dev)
  135. {
  136. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  137. u8 *regs = priv->regs;
  138. int ret;
  139. /* Lock settings */
  140. setbits_le32(regs + 0x0a248, (1 << 31));
  141. setbits_le32(regs + 0x0a004, (1 << 4));
  142. setbits_le32(regs + 0x0a080, (1 << 2));
  143. setbits_le32(regs + 0x0a180, (1 << 31));
  144. /* Disable Force Wake */
  145. writel(0x00010000, regs + 0xa188);
  146. ret = poll32(regs + 0x130044, 1, 0);
  147. if (ret)
  148. goto err;
  149. writel(0x00000001, regs + 0xa188);
  150. /* Enable power well for DP and Audio */
  151. setbits_le32(regs + 0x45400, (1 << 31));
  152. ret = poll32(regs + 0x45400, 1 << 30, 1 << 30);
  153. if (ret)
  154. goto err;
  155. return 0;
  156. err:
  157. debug("%s: ret=%d\n", __func__, ret);
  158. return ret;
  159. };
  160. static int broadwell_early_init(struct udevice *dev)
  161. {
  162. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  163. u8 *regs = priv->regs;
  164. int ret;
  165. /* Enable Force Wake */
  166. writel(0x00010001, regs + 0xa188);
  167. ret = poll32(regs + 0x130044, 1, 1);
  168. if (ret)
  169. goto err;
  170. /* Enable push bus metric control and shift */
  171. writel(0x00000004, regs + 0xa248);
  172. writel(0x000000ff, regs + 0xa250);
  173. writel(0x00000010, regs + 0xa25c);
  174. /* GFXPAUSE settings (set based on stepping) */
  175. /* ECO Settings */
  176. writel(0x45200000, regs + 0xa180);
  177. /* Enable DOP Clock Gating */
  178. writel(0x000000fd, regs + 0x9424);
  179. /* Enable Unit Level Clock Gating */
  180. writel(0x00000000, regs + 0x9400);
  181. writel(0x40401000, regs + 0x9404);
  182. writel(0x00000000, regs + 0x9408);
  183. writel(0x02000001, regs + 0x940c);
  184. writel(0x0000000a, regs + 0x1a054);
  185. /* Video Frequency Request */
  186. writel(0x08000000, regs + 0xa00c);
  187. writel(0x00000009, regs + 0x138158);
  188. writel(0x0000000d, regs + 0x13815c);
  189. /*
  190. * RC6 Settings
  191. */
  192. /* Wake Rate Limits */
  193. clrsetbits_le32(regs + 0x0a090, ~0, 0);
  194. setbits_le32(regs + 0x0a098, 0x03e80000);
  195. setbits_le32(regs + 0x0a09c, 0x00280000);
  196. setbits_le32(regs + 0x0a0a8, 0x0001e848);
  197. setbits_le32(regs + 0x0a0ac, 0x00000019);
  198. /* Render/Video/Blitter Idle Max Count */
  199. writel(0x0000000a, regs + 0x02054);
  200. writel(0x0000000a, regs + 0x12054);
  201. writel(0x0000000a, regs + 0x22054);
  202. /* RC Sleep / RCx Thresholds */
  203. setbits_le32(regs + 0x0a0b0, 0x00000000);
  204. setbits_le32(regs + 0x0a0b8, 0x00000271);
  205. /* RP Settings */
  206. setbits_le32(regs + 0x0a010, 0x000f4240);
  207. setbits_le32(regs + 0x0a014, 0x12060000);
  208. setbits_le32(regs + 0x0a02c, 0x0000e808);
  209. setbits_le32(regs + 0x0a030, 0x0003bd08);
  210. setbits_le32(regs + 0x0a068, 0x000101d0);
  211. setbits_le32(regs + 0x0a06c, 0x00055730);
  212. setbits_le32(regs + 0x0a070, 0x0000000a);
  213. setbits_le32(regs + 0x0a168, 0x00000006);
  214. /* RP Control */
  215. writel(0x00000b92, regs + 0xa024);
  216. /* HW RC6 Control */
  217. writel(0x90040000, regs + 0xa090);
  218. /* Set RC6 VIDs */
  219. ret = poll32(regs + 0x138124, (1 << 31), 0);
  220. if (ret)
  221. goto err;
  222. writel(0, regs + 0x138128);
  223. writel(0x80000004, regs + 0x138124);
  224. ret = poll32(regs + 0x138124, (1 << 31), 0);
  225. if (ret)
  226. goto err;
  227. /* Enable PM Interrupts */
  228. writel(0x03000076, regs + 0x4402c);
  229. /* Enable RC6 in idle */
  230. writel(0x00040000, regs + 0xa094);
  231. return 0;
  232. err:
  233. debug("%s: ret=%d\n", __func__, ret);
  234. return ret;
  235. }
  236. static int broadwell_late_init(struct udevice *dev)
  237. {
  238. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  239. u8 *regs = priv->regs;
  240. int ret;
  241. /* Lock settings */
  242. setbits_le32(regs + 0x0a248, 1 << 31);
  243. setbits_le32(regs + 0x0a000, 1 << 18);
  244. setbits_le32(regs + 0x0a180, 1 << 31);
  245. /* Disable Force Wake */
  246. writel(0x00010000, regs + 0xa188);
  247. ret = poll32(regs + 0x130044, 1, 0);
  248. if (ret)
  249. goto err;
  250. /* Enable power well for DP and Audio */
  251. setbits_le32(regs + 0x45400, 1 << 31);
  252. ret = poll32(regs + 0x45400, 1 << 30, 1 << 30);
  253. if (ret)
  254. goto err;
  255. return 0;
  256. err:
  257. debug("%s: ret=%d\n", __func__, ret);
  258. return ret;
  259. };
  260. static unsigned long gtt_read(struct broadwell_igd_priv *priv,
  261. unsigned long reg)
  262. {
  263. return readl(priv->regs + reg);
  264. }
  265. static void gtt_write(struct broadwell_igd_priv *priv, unsigned long reg,
  266. unsigned long data)
  267. {
  268. writel(data, priv->regs + reg);
  269. }
  270. static inline void gtt_clrsetbits(struct broadwell_igd_priv *priv, u32 reg,
  271. u32 bic, u32 or)
  272. {
  273. clrsetbits_le32(priv->regs + reg, bic, or);
  274. }
  275. static int gtt_poll(struct broadwell_igd_priv *priv, u32 reg, u32 mask,
  276. u32 value)
  277. {
  278. unsigned try = GT_RETRY;
  279. u32 data;
  280. while (try--) {
  281. data = gtt_read(priv, reg);
  282. if ((data & mask) == value)
  283. return 0;
  284. udelay(10);
  285. }
  286. debug("GT init timeout\n");
  287. return -ETIMEDOUT;
  288. }
  289. static void igd_setup_panel(struct udevice *dev)
  290. {
  291. struct broadwell_igd_plat *plat = dev_get_platdata(dev);
  292. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  293. u32 reg32;
  294. /* Setup Digital Port Hotplug */
  295. reg32 = (plat->dp_hotplug[0] & 0x7) << 2;
  296. reg32 |= (plat->dp_hotplug[1] & 0x7) << 10;
  297. reg32 |= (plat->dp_hotplug[2] & 0x7) << 18;
  298. gtt_write(priv, PCH_PORT_HOTPLUG, reg32);
  299. /* Setup Panel Power On Delays */
  300. reg32 = (plat->port_select & 0x3) << 30;
  301. reg32 |= (plat->power_up_delay & 0x1fff) << 16;
  302. reg32 |= (plat->power_backlight_on_delay & 0x1fff);
  303. gtt_write(priv, PCH_PP_ON_DELAYS, reg32);
  304. /* Setup Panel Power Off Delays */
  305. reg32 = (plat->power_down_delay & 0x1fff) << 16;
  306. reg32 |= (plat->power_backlight_off_delay & 0x1fff);
  307. gtt_write(priv, PCH_PP_OFF_DELAYS, reg32);
  308. /* Setup Panel Power Cycle Delay */
  309. if (plat->power_cycle_delay) {
  310. reg32 = gtt_read(priv, PCH_PP_DIVISOR);
  311. reg32 &= ~0xff;
  312. reg32 |= plat->power_cycle_delay & 0xff;
  313. gtt_write(priv, PCH_PP_DIVISOR, reg32);
  314. }
  315. /* Enable Backlight if needed */
  316. if (plat->cpu_backlight) {
  317. gtt_write(priv, BLC_PWM_CPU_CTL2, BLC_PWM2_ENABLE);
  318. gtt_write(priv, BLC_PWM_CPU_CTL, plat->cpu_backlight);
  319. }
  320. if (plat->pch_backlight) {
  321. gtt_write(priv, BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE);
  322. gtt_write(priv, BLC_PWM_PCH_CTL2, plat->pch_backlight);
  323. }
  324. }
  325. static int igd_cdclk_init_haswell(struct udevice *dev)
  326. {
  327. struct broadwell_igd_plat *plat = dev_get_platdata(dev);
  328. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  329. int cdclk = plat->cdclk;
  330. u16 devid;
  331. int gpu_is_ulx = 0;
  332. u32 dpdiv, lpcll;
  333. int ret;
  334. dm_pci_read_config16(dev, PCI_DEVICE_ID, &devid);
  335. /* Check for ULX GT1 or GT2 */
  336. if (devid == 0x0a0e || devid == 0x0a1e)
  337. gpu_is_ulx = 1;
  338. /* 675MHz is not supported on haswell */
  339. if (cdclk == GT_CDCLK_675)
  340. cdclk = GT_CDCLK_337;
  341. /* If CD clock is fixed or ULT then set to 450MHz */
  342. if ((gtt_read(priv, 0x42014) & 0x1000000) || cpu_is_ult())
  343. cdclk = GT_CDCLK_450;
  344. /* 540MHz is not supported on ULX */
  345. if (gpu_is_ulx && cdclk == GT_CDCLK_540)
  346. cdclk = GT_CDCLK_337;
  347. /* 337.5MHz is not supported on non-ULT/ULX */
  348. if (!gpu_is_ulx && !cpu_is_ult() && cdclk == GT_CDCLK_337)
  349. cdclk = GT_CDCLK_450;
  350. /* Set variables based on CD Clock setting */
  351. switch (cdclk) {
  352. case GT_CDCLK_337:
  353. dpdiv = 169;
  354. lpcll = (1 << 26);
  355. break;
  356. case GT_CDCLK_450:
  357. dpdiv = 225;
  358. lpcll = 0;
  359. break;
  360. case GT_CDCLK_540:
  361. dpdiv = 270;
  362. lpcll = (1 << 26);
  363. break;
  364. default:
  365. ret = -EDOM;
  366. goto err;
  367. }
  368. /* Set LPCLL_CTL CD Clock Frequency Select */
  369. gtt_clrsetbits(priv, 0x130040, ~0xf3ffffff, lpcll);
  370. /* ULX: Inform power controller of selected frequency */
  371. if (gpu_is_ulx) {
  372. if (cdclk == GT_CDCLK_450)
  373. gtt_write(priv, 0x138128, 0x00000000); /* 450MHz */
  374. else
  375. gtt_write(priv, 0x138128, 0x00000001); /* 337.5MHz */
  376. gtt_write(priv, 0x13812c, 0x00000000);
  377. gtt_write(priv, 0x138124, 0x80000017);
  378. }
  379. /* Set CPU DP AUX 2X bit clock dividers */
  380. gtt_clrsetbits(priv, 0x64010, ~0xfffff800, dpdiv);
  381. gtt_clrsetbits(priv, 0x64810, ~0xfffff800, dpdiv);
  382. return 0;
  383. err:
  384. debug("%s: ret=%d\n", __func__, ret);
  385. return ret;
  386. }
  387. static int igd_cdclk_init_broadwell(struct udevice *dev)
  388. {
  389. struct broadwell_igd_plat *plat = dev_get_platdata(dev);
  390. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  391. int cdclk = plat->cdclk;
  392. u32 dpdiv, lpcll, pwctl, cdset;
  393. int ret;
  394. /* Inform power controller of upcoming frequency change */
  395. gtt_write(priv, 0x138128, 0);
  396. gtt_write(priv, 0x13812c, 0);
  397. gtt_write(priv, 0x138124, 0x80000018);
  398. /* Poll GT driver mailbox for run/busy clear */
  399. if (gtt_poll(priv, 0x138124, 1 << 31, 0 << 31))
  400. cdclk = GT_CDCLK_450;
  401. if (gtt_read(priv, 0x42014) & 0x1000000) {
  402. /* If CD clock is fixed then set to 450MHz */
  403. cdclk = GT_CDCLK_450;
  404. } else {
  405. /* Program CD clock to highest supported freq */
  406. if (cpu_is_ult())
  407. cdclk = GT_CDCLK_540;
  408. else
  409. cdclk = GT_CDCLK_675;
  410. }
  411. /* CD clock frequency 675MHz not supported on ULT */
  412. if (cpu_is_ult() && cdclk == GT_CDCLK_675)
  413. cdclk = GT_CDCLK_540;
  414. /* Set variables based on CD Clock setting */
  415. switch (cdclk) {
  416. case GT_CDCLK_337:
  417. cdset = 337;
  418. lpcll = (1 << 27);
  419. pwctl = 2;
  420. dpdiv = 169;
  421. break;
  422. case GT_CDCLK_450:
  423. cdset = 449;
  424. lpcll = 0;
  425. pwctl = 0;
  426. dpdiv = 225;
  427. break;
  428. case GT_CDCLK_540:
  429. cdset = 539;
  430. lpcll = (1 << 26);
  431. pwctl = 1;
  432. dpdiv = 270;
  433. break;
  434. case GT_CDCLK_675:
  435. cdset = 674;
  436. lpcll = (1 << 26) | (1 << 27);
  437. pwctl = 3;
  438. dpdiv = 338;
  439. break;
  440. default:
  441. ret = -EDOM;
  442. goto err;
  443. }
  444. debug("%s: frequency = %d\n", __func__, cdclk);
  445. /* Set LPCLL_CTL CD Clock Frequency Select */
  446. gtt_clrsetbits(priv, 0x130040, ~0xf3ffffff, lpcll);
  447. /* Inform power controller of selected frequency */
  448. gtt_write(priv, 0x138128, pwctl);
  449. gtt_write(priv, 0x13812c, 0);
  450. gtt_write(priv, 0x138124, 0x80000017);
  451. /* Program CD Clock Frequency */
  452. gtt_clrsetbits(priv, 0x46200, ~0xfffffc00, cdset);
  453. /* Set CPU DP AUX 2X bit clock dividers */
  454. gtt_clrsetbits(priv, 0x64010, ~0xfffff800, dpdiv);
  455. gtt_clrsetbits(priv, 0x64810, ~0xfffff800, dpdiv);
  456. return 0;
  457. err:
  458. debug("%s: ret=%d\n", __func__, ret);
  459. return ret;
  460. }
  461. u8 systemagent_revision(struct udevice *bus)
  462. {
  463. ulong val;
  464. pci_bus_read_config(bus, PCI_BDF(0, 0, 0), PCI_REVISION_ID, &val,
  465. PCI_SIZE_32);
  466. return val;
  467. }
  468. static int igd_pre_init(struct udevice *dev, bool is_broadwell)
  469. {
  470. struct broadwell_igd_plat *plat = dev_get_platdata(dev);
  471. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  472. u32 rp1_gfx_freq;
  473. int ret;
  474. mdelay(plat->pre_graphics_delay);
  475. /* Early init steps */
  476. if (is_broadwell) {
  477. ret = broadwell_early_init(dev);
  478. if (ret)
  479. goto err;
  480. /* Set GFXPAUSE based on stepping */
  481. if (cpu_get_stepping() <= (CPUID_BROADWELL_E0 & 0xf) &&
  482. systemagent_revision(pci_get_controller(dev)) <= 9) {
  483. gtt_write(priv, 0xa000, 0x300ff);
  484. } else {
  485. gtt_write(priv, 0xa000, 0x30020);
  486. }
  487. } else {
  488. ret = haswell_early_init(dev);
  489. if (ret)
  490. goto err;
  491. }
  492. /* Set RP1 graphics frequency */
  493. rp1_gfx_freq = (readl(MCHBAR_REG(0x5998)) >> 8) & 0xff;
  494. gtt_write(priv, 0xa008, rp1_gfx_freq << 24);
  495. /* Post VBIOS panel setup */
  496. igd_setup_panel(dev);
  497. return 0;
  498. err:
  499. debug("%s: ret=%d\n", __func__, ret);
  500. return ret;
  501. }
  502. static int igd_post_init(struct udevice *dev, bool is_broadwell)
  503. {
  504. int ret;
  505. /* Late init steps */
  506. if (is_broadwell) {
  507. ret = igd_cdclk_init_broadwell(dev);
  508. if (ret)
  509. return ret;
  510. ret = broadwell_late_init(dev);
  511. if (ret)
  512. return ret;
  513. } else {
  514. igd_cdclk_init_haswell(dev);
  515. ret = haswell_late_init(dev);
  516. if (ret)
  517. return ret;
  518. }
  519. return 0;
  520. }
  521. static int broadwell_igd_int15_handler(void)
  522. {
  523. int res = 0;
  524. debug("%s: INT15 function %04x!\n", __func__, M.x86.R_AX);
  525. switch (M.x86.R_AX) {
  526. case 0x5f35:
  527. /*
  528. * Boot Display Device Hook:
  529. * bit 0 = CRT
  530. * bit 1 = TV (eDP)
  531. * bit 2 = EFP
  532. * bit 3 = LFP
  533. * bit 4 = CRT2
  534. * bit 5 = TV2 (eDP)
  535. * bit 6 = EFP2
  536. * bit 7 = LFP2
  537. */
  538. M.x86.R_AX = 0x005f;
  539. M.x86.R_CX = 0x0000; /* Use video bios default */
  540. res = 1;
  541. break;
  542. default:
  543. debug("Unknown INT15 function %04x!\n", M.x86.R_AX);
  544. break;
  545. }
  546. return res;
  547. }
  548. static int broadwell_igd_probe(struct udevice *dev)
  549. {
  550. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  551. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  552. bool is_broadwell;
  553. int ret;
  554. if (!ll_boot_init()) {
  555. /*
  556. * If we are running from EFI or coreboot, this driver can't
  557. * work.
  558. */
  559. printf("Not available (previous bootloader prevents it)\n");
  560. return -EPERM;
  561. }
  562. is_broadwell = cpu_get_family_model() == BROADWELL_FAMILY_ULT;
  563. bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
  564. debug("%s: is_broadwell=%d\n", __func__, is_broadwell);
  565. ret = igd_pre_init(dev, is_broadwell);
  566. if (!ret) {
  567. ret = vbe_setup_video(dev, broadwell_igd_int15_handler);
  568. if (ret)
  569. debug("failed to run video BIOS: %d\n", ret);
  570. }
  571. if (!ret)
  572. ret = igd_post_init(dev, is_broadwell);
  573. bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
  574. if (ret)
  575. return ret;
  576. /* Use write-combining for the graphics memory, 256MB */
  577. ret = mtrr_add_request(MTRR_TYPE_WRCOMB, plat->base, 256 << 20);
  578. if (!ret)
  579. ret = mtrr_commit(true);
  580. if (ret && ret != -ENOSYS) {
  581. printf("Failed to add MTRR: Display will be slow (err %d)\n",
  582. ret);
  583. }
  584. debug("fb=%lx, size %x, display size=%d %d %d\n", plat->base,
  585. plat->size, uc_priv->xsize, uc_priv->ysize, uc_priv->bpix);
  586. return 0;
  587. }
  588. static int broadwell_igd_ofdata_to_platdata(struct udevice *dev)
  589. {
  590. struct broadwell_igd_plat *plat = dev_get_platdata(dev);
  591. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  592. int node = dev_of_offset(dev);
  593. const void *blob = gd->fdt_blob;
  594. if (fdtdec_get_int_array(blob, node, "intel,dp-hotplug",
  595. plat->dp_hotplug,
  596. ARRAY_SIZE(plat->dp_hotplug)))
  597. return -EINVAL;
  598. plat->port_select = fdtdec_get_int(blob, node, "intel,port-select", 0);
  599. plat->power_cycle_delay = fdtdec_get_int(blob, node,
  600. "intel,power-cycle-delay", 0);
  601. plat->power_up_delay = fdtdec_get_int(blob, node,
  602. "intel,power-up-delay", 0);
  603. plat->power_down_delay = fdtdec_get_int(blob, node,
  604. "intel,power-down-delay", 0);
  605. plat->power_backlight_on_delay = fdtdec_get_int(blob, node,
  606. "intel,power-backlight-on-delay", 0);
  607. plat->power_backlight_off_delay = fdtdec_get_int(blob, node,
  608. "intel,power-backlight-off-delay", 0);
  609. plat->cpu_backlight = fdtdec_get_int(blob, node,
  610. "intel,cpu-backlight", 0);
  611. plat->pch_backlight = fdtdec_get_int(blob, node,
  612. "intel,pch-backlight", 0);
  613. plat->pre_graphics_delay = fdtdec_get_int(blob, node,
  614. "intel,pre-graphics-delay", 0);
  615. priv->regs = (u8 *)dm_pci_read_bar32(dev, 0);
  616. debug("%s: regs at %p\n", __func__, priv->regs);
  617. debug("dp_hotplug %d %d %d\n", plat->dp_hotplug[0], plat->dp_hotplug[1],
  618. plat->dp_hotplug[2]);
  619. debug("port_select = %d\n", plat->port_select);
  620. debug("power_up_delay = %d\n", plat->power_up_delay);
  621. debug("power_backlight_on_delay = %d\n",
  622. plat->power_backlight_on_delay);
  623. debug("power_down_delay = %d\n", plat->power_down_delay);
  624. debug("power_backlight_off_delay = %d\n",
  625. plat->power_backlight_off_delay);
  626. debug("power_cycle_delay = %d\n", plat->power_cycle_delay);
  627. debug("cpu_backlight = %x\n", plat->cpu_backlight);
  628. debug("pch_backlight = %x\n", plat->pch_backlight);
  629. debug("cdclk = %d\n", plat->cdclk);
  630. debug("pre_graphics_delay = %d\n", plat->pre_graphics_delay);
  631. return 0;
  632. }
  633. static const struct video_ops broadwell_igd_ops = {
  634. };
  635. static const struct udevice_id broadwell_igd_ids[] = {
  636. { .compatible = "intel,broadwell-igd" },
  637. { }
  638. };
  639. U_BOOT_DRIVER(broadwell_igd) = {
  640. .name = "broadwell_igd",
  641. .id = UCLASS_VIDEO,
  642. .of_match = broadwell_igd_ids,
  643. .ops = &broadwell_igd_ops,
  644. .ofdata_to_platdata = broadwell_igd_ofdata_to_platdata,
  645. .probe = broadwell_igd_probe,
  646. .priv_auto_alloc_size = sizeof(struct broadwell_igd_priv),
  647. .platdata_auto_alloc_size = sizeof(struct broadwell_igd_plat),
  648. };