tsc_timer.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2012 The Chromium OS Authors.
  4. *
  5. * TSC calibration codes are adapted from Linux kernel
  6. * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c
  7. */
  8. #include <common.h>
  9. #include <bootstage.h>
  10. #include <dm.h>
  11. #include <malloc.h>
  12. #include <time.h>
  13. #include <timer.h>
  14. #include <asm/cpu.h>
  15. #include <asm/io.h>
  16. #include <asm/i8254.h>
  17. #include <asm/ibmpc.h>
  18. #include <asm/msr.h>
  19. #include <asm/u-boot-x86.h>
  20. #define MAX_NUM_FREQS 9
  21. #define INTEL_FAM6_SKYLAKE_MOBILE 0x4E
  22. #define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */
  23. #define INTEL_FAM6_SKYLAKE_DESKTOP 0x5E
  24. #define INTEL_FAM6_ATOM_GOLDMONT_X 0x5F /* Denverton */
  25. #define INTEL_FAM6_KABYLAKE_MOBILE 0x8E
  26. #define INTEL_FAM6_KABYLAKE_DESKTOP 0x9E
  27. DECLARE_GLOBAL_DATA_PTR;
  28. /*
  29. * native_calibrate_tsc
  30. * Determine TSC frequency via CPUID, else return 0.
  31. */
  32. static unsigned long native_calibrate_tsc(void)
  33. {
  34. struct cpuid_result tsc_info;
  35. unsigned int crystal_freq;
  36. if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
  37. return 0;
  38. if (cpuid_eax(0) < 0x15)
  39. return 0;
  40. tsc_info = cpuid(0x15);
  41. if (tsc_info.ebx == 0 || tsc_info.eax == 0)
  42. return 0;
  43. crystal_freq = tsc_info.ecx / 1000;
  44. if (!CONFIG_IS_ENABLED(X86_TSC_TIMER_NATIVE) && !crystal_freq) {
  45. switch (gd->arch.x86_model) {
  46. case INTEL_FAM6_SKYLAKE_MOBILE:
  47. case INTEL_FAM6_SKYLAKE_DESKTOP:
  48. case INTEL_FAM6_KABYLAKE_MOBILE:
  49. case INTEL_FAM6_KABYLAKE_DESKTOP:
  50. crystal_freq = 24000; /* 24.0 MHz */
  51. break;
  52. case INTEL_FAM6_ATOM_GOLDMONT_X:
  53. crystal_freq = 25000; /* 25.0 MHz */
  54. break;
  55. case INTEL_FAM6_ATOM_GOLDMONT:
  56. crystal_freq = 19200; /* 19.2 MHz */
  57. break;
  58. default:
  59. return 0;
  60. }
  61. }
  62. return (crystal_freq * tsc_info.ebx / tsc_info.eax) / 1000;
  63. }
  64. static unsigned long cpu_mhz_from_cpuid(void)
  65. {
  66. if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
  67. return 0;
  68. if (cpuid_eax(0) < 0x16)
  69. return 0;
  70. return cpuid_eax(0x16);
  71. }
  72. /*
  73. * According to Intel 64 and IA-32 System Programming Guide,
  74. * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
  75. * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
  76. * Unfortunately some Intel Atom SoCs aren't quite compliant to this,
  77. * so we need manually differentiate SoC families. This is what the
  78. * field msr_plat does.
  79. */
  80. struct freq_desc {
  81. u8 x86_family; /* CPU family */
  82. u8 x86_model; /* model */
  83. /* 2: use 100MHz, 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
  84. u8 msr_plat;
  85. u32 freqs[MAX_NUM_FREQS];
  86. };
  87. static struct freq_desc freq_desc_tables[] = {
  88. /* PNW */
  89. { 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200, 0 } },
  90. /* CLV+ */
  91. { 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200, 0 } },
  92. /* TNG - Intel Atom processor Z3400 series */
  93. { 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0, 0 } },
  94. /* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */
  95. { 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0, 0 } },
  96. /* ANN - Intel Atom processor Z3500 series */
  97. { 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0, 0 } },
  98. /* AMT - Intel Atom processor X7-Z8000 and X5-Z8000 series */
  99. { 6, 0x4c, 1, { 83300, 100000, 133300, 116700,
  100. 80000, 93300, 90000, 88900, 87500 } },
  101. /* Ivybridge */
  102. { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
  103. };
  104. static int match_cpu(u8 family, u8 model)
  105. {
  106. int i;
  107. for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) {
  108. if ((family == freq_desc_tables[i].x86_family) &&
  109. (model == freq_desc_tables[i].x86_model))
  110. return i;
  111. }
  112. return -1;
  113. }
  114. /* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
  115. #define id_to_freq(cpu_index, freq_id) \
  116. (freq_desc_tables[cpu_index].freqs[freq_id])
  117. /*
  118. * TSC on Intel Atom SoCs capable of determining TSC frequency by MSR is
  119. * reliable and the frequency is known (provided by HW).
  120. *
  121. * On these platforms PIT/HPET is generally not available so calibration won't
  122. * work at all and there is no other clocksource to act as a watchdog for the
  123. * TSC, so we have no other choice than to trust it.
  124. *
  125. * Returns the TSC frequency in MHz or 0 if HW does not provide it.
  126. */
  127. static unsigned long __maybe_unused cpu_mhz_from_msr(void)
  128. {
  129. u32 lo, hi, ratio, freq_id, freq;
  130. unsigned long res;
  131. int cpu_index;
  132. if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
  133. return 0;
  134. cpu_index = match_cpu(gd->arch.x86, gd->arch.x86_model);
  135. if (cpu_index < 0)
  136. return 0;
  137. if (freq_desc_tables[cpu_index].msr_plat) {
  138. rdmsr(MSR_PLATFORM_INFO, lo, hi);
  139. ratio = (lo >> 8) & 0xff;
  140. } else {
  141. rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
  142. ratio = (hi >> 8) & 0x1f;
  143. }
  144. debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
  145. if (freq_desc_tables[cpu_index].msr_plat == 2) {
  146. /* TODO: Figure out how best to deal with this */
  147. freq = 100000;
  148. debug("Using frequency: %u KHz\n", freq);
  149. } else {
  150. /* Get FSB FREQ ID */
  151. rdmsr(MSR_FSB_FREQ, lo, hi);
  152. freq_id = lo & 0x7;
  153. freq = id_to_freq(cpu_index, freq_id);
  154. debug("Resolved frequency ID: %u, frequency: %u KHz\n",
  155. freq_id, freq);
  156. }
  157. /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
  158. res = freq * ratio / 1000;
  159. debug("TSC runs at %lu MHz\n", res);
  160. return res;
  161. }
  162. /*
  163. * This reads the current MSB of the PIT counter, and
  164. * checks if we are running on sufficiently fast and
  165. * non-virtualized hardware.
  166. *
  167. * Our expectations are:
  168. *
  169. * - the PIT is running at roughly 1.19MHz
  170. *
  171. * - each IO is going to take about 1us on real hardware,
  172. * but we allow it to be much faster (by a factor of 10) or
  173. * _slightly_ slower (ie we allow up to a 2us read+counter
  174. * update - anything else implies a unacceptably slow CPU
  175. * or PIT for the fast calibration to work.
  176. *
  177. * - with 256 PIT ticks to read the value, we have 214us to
  178. * see the same MSB (and overhead like doing a single TSC
  179. * read per MSB value etc).
  180. *
  181. * - We're doing 2 reads per loop (LSB, MSB), and we expect
  182. * them each to take about a microsecond on real hardware.
  183. * So we expect a count value of around 100. But we'll be
  184. * generous, and accept anything over 50.
  185. *
  186. * - if the PIT is stuck, and we see *many* more reads, we
  187. * return early (and the next caller of pit_expect_msb()
  188. * then consider it a failure when they don't see the
  189. * next expected value).
  190. *
  191. * These expectations mean that we know that we have seen the
  192. * transition from one expected value to another with a fairly
  193. * high accuracy, and we didn't miss any events. We can thus
  194. * use the TSC value at the transitions to calculate a pretty
  195. * good value for the TSC frequencty.
  196. */
  197. static inline int pit_verify_msb(unsigned char val)
  198. {
  199. /* Ignore LSB */
  200. inb(0x42);
  201. return inb(0x42) == val;
  202. }
  203. static inline int pit_expect_msb(unsigned char val, u64 *tscp,
  204. unsigned long *deltap)
  205. {
  206. int count;
  207. u64 tsc = 0, prev_tsc = 0;
  208. for (count = 0; count < 50000; count++) {
  209. if (!pit_verify_msb(val))
  210. break;
  211. prev_tsc = tsc;
  212. tsc = rdtsc();
  213. }
  214. *deltap = rdtsc() - prev_tsc;
  215. *tscp = tsc;
  216. /*
  217. * We require _some_ success, but the quality control
  218. * will be based on the error terms on the TSC values.
  219. */
  220. return count > 5;
  221. }
  222. /*
  223. * How many MSB values do we want to see? We aim for
  224. * a maximum error rate of 500ppm (in practice the
  225. * real error is much smaller), but refuse to spend
  226. * more than 50ms on it.
  227. */
  228. #define MAX_QUICK_PIT_MS 50
  229. #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
  230. static unsigned long __maybe_unused quick_pit_calibrate(void)
  231. {
  232. int i;
  233. u64 tsc, delta;
  234. unsigned long d1, d2;
  235. /* Set the Gate high, disable speaker */
  236. outb((inb(0x61) & ~0x02) | 0x01, 0x61);
  237. /*
  238. * Counter 2, mode 0 (one-shot), binary count
  239. *
  240. * NOTE! Mode 2 decrements by two (and then the
  241. * output is flipped each time, giving the same
  242. * final output frequency as a decrement-by-one),
  243. * so mode 0 is much better when looking at the
  244. * individual counts.
  245. */
  246. outb(0xb0, 0x43);
  247. /* Start at 0xffff */
  248. outb(0xff, 0x42);
  249. outb(0xff, 0x42);
  250. /*
  251. * The PIT starts counting at the next edge, so we
  252. * need to delay for a microsecond. The easiest way
  253. * to do that is to just read back the 16-bit counter
  254. * once from the PIT.
  255. */
  256. pit_verify_msb(0);
  257. if (pit_expect_msb(0xff, &tsc, &d1)) {
  258. for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
  259. if (!pit_expect_msb(0xff-i, &delta, &d2))
  260. break;
  261. /*
  262. * Iterate until the error is less than 500 ppm
  263. */
  264. delta -= tsc;
  265. if (d1+d2 >= delta >> 11)
  266. continue;
  267. /*
  268. * Check the PIT one more time to verify that
  269. * all TSC reads were stable wrt the PIT.
  270. *
  271. * This also guarantees serialization of the
  272. * last cycle read ('d2') in pit_expect_msb.
  273. */
  274. if (!pit_verify_msb(0xfe - i))
  275. break;
  276. goto success;
  277. }
  278. }
  279. debug("Fast TSC calibration failed\n");
  280. return 0;
  281. success:
  282. /*
  283. * Ok, if we get here, then we've seen the
  284. * MSB of the PIT decrement 'i' times, and the
  285. * error has shrunk to less than 500 ppm.
  286. *
  287. * As a result, we can depend on there not being
  288. * any odd delays anywhere, and the TSC reads are
  289. * reliable (within the error).
  290. *
  291. * kHz = ticks / time-in-seconds / 1000;
  292. * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
  293. * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
  294. */
  295. delta *= PIT_TICK_RATE;
  296. delta /= (i*256*1000);
  297. debug("Fast TSC calibration using PIT\n");
  298. return delta / 1000;
  299. }
  300. /* Get the speed of the TSC timer in MHz */
  301. unsigned notrace long get_tbclk_mhz(void)
  302. {
  303. return get_tbclk() / 1000000;
  304. }
  305. static ulong get_ms_timer(void)
  306. {
  307. return (get_ticks() * 1000) / get_tbclk();
  308. }
  309. ulong get_timer(ulong base)
  310. {
  311. return get_ms_timer() - base;
  312. }
  313. ulong notrace timer_get_us(void)
  314. {
  315. return get_ticks() / get_tbclk_mhz();
  316. }
  317. ulong timer_get_boot_us(void)
  318. {
  319. return timer_get_us();
  320. }
  321. void __udelay(unsigned long usec)
  322. {
  323. u64 now = get_ticks();
  324. u64 stop;
  325. stop = now + usec * get_tbclk_mhz();
  326. while ((int64_t)(stop - get_ticks()) > 0)
  327. #if defined(CONFIG_QEMU) && defined(CONFIG_SMP)
  328. /*
  329. * Add a 'pause' instruction on qemu target,
  330. * to give other VCPUs a chance to run.
  331. */
  332. asm volatile("pause");
  333. #else
  334. ;
  335. #endif
  336. }
  337. static int tsc_timer_get_count(struct udevice *dev, u64 *count)
  338. {
  339. u64 now_tick = rdtsc();
  340. *count = now_tick - gd->arch.tsc_base;
  341. return 0;
  342. }
  343. static void tsc_timer_ensure_setup(bool early)
  344. {
  345. if (gd->arch.tsc_inited)
  346. return;
  347. if (IS_ENABLED(CONFIG_X86_TSC_READ_BASE))
  348. gd->arch.tsc_base = rdtsc();
  349. if (!gd->arch.clock_rate) {
  350. unsigned long fast_calibrate;
  351. fast_calibrate = native_calibrate_tsc();
  352. if (fast_calibrate)
  353. goto done;
  354. /* Reduce code size by dropping other methods */
  355. if (CONFIG_IS_ENABLED(X86_TSC_TIMER_NATIVE))
  356. panic("no timer");
  357. fast_calibrate = cpu_mhz_from_cpuid();
  358. if (fast_calibrate)
  359. goto done;
  360. fast_calibrate = cpu_mhz_from_msr();
  361. if (fast_calibrate)
  362. goto done;
  363. fast_calibrate = quick_pit_calibrate();
  364. if (fast_calibrate)
  365. goto done;
  366. if (early)
  367. fast_calibrate = CONFIG_X86_TSC_TIMER_EARLY_FREQ;
  368. else
  369. return;
  370. done:
  371. gd->arch.clock_rate = fast_calibrate * 1000000;
  372. }
  373. gd->arch.tsc_inited = true;
  374. }
  375. static int tsc_timer_probe(struct udevice *dev)
  376. {
  377. struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  378. /* Try hardware calibration first */
  379. tsc_timer_ensure_setup(false);
  380. if (!gd->arch.clock_rate) {
  381. /*
  382. * Use the clock frequency specified in the
  383. * device tree as last resort
  384. */
  385. if (!uc_priv->clock_rate)
  386. panic("TSC frequency is ZERO");
  387. } else {
  388. uc_priv->clock_rate = gd->arch.clock_rate;
  389. }
  390. return 0;
  391. }
  392. unsigned long notrace timer_early_get_rate(void)
  393. {
  394. /*
  395. * When TSC timer is used as the early timer, be warned that the timer
  396. * clock rate can only be calibrated via some hardware ways. Specifying
  397. * it in the device tree won't work for the early timer.
  398. */
  399. tsc_timer_ensure_setup(true);
  400. return gd->arch.clock_rate;
  401. }
  402. u64 notrace timer_early_get_count(void)
  403. {
  404. tsc_timer_ensure_setup(true);
  405. return rdtsc() - gd->arch.tsc_base;
  406. }
  407. static const struct timer_ops tsc_timer_ops = {
  408. .get_count = tsc_timer_get_count,
  409. };
  410. static const struct udevice_id tsc_timer_ids[] = {
  411. { .compatible = "x86,tsc-timer", },
  412. { }
  413. };
  414. U_BOOT_DRIVER(tsc_timer) = {
  415. .name = "tsc_timer",
  416. .id = UCLASS_TIMER,
  417. .of_match = tsc_timer_ids,
  418. .probe = tsc_timer_probe,
  419. .ops = &tsc_timer_ops,
  420. };