cadence-ttc.c 2.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 Xilinx, Inc. (Michal Simek)
  4. */
  5. #include <common.h>
  6. #include <bootstage.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <timer.h>
  10. #include <asm/io.h>
  11. #include <linux/err.h>
  12. #define CNT_CNTRL_RESET BIT(4)
  13. struct cadence_ttc_regs {
  14. u32 clk_cntrl1; /* 0x0 - Clock Control 1 */
  15. u32 clk_cntrl2; /* 0x4 - Clock Control 2 */
  16. u32 clk_cntrl3; /* 0x8 - Clock Control 3 */
  17. u32 counter_cntrl1; /* 0xC - Counter Control 1 */
  18. u32 counter_cntrl2; /* 0x10 - Counter Control 2 */
  19. u32 counter_cntrl3; /* 0x14 - Counter Control 3 */
  20. u32 counter_val1; /* 0x18 - Counter Control 1 */
  21. u32 counter_val2; /* 0x1C - Counter Control 2 */
  22. u32 counter_val3; /* 0x20 - Counter Control 3 */
  23. u32 reserved[15];
  24. u32 interrupt_enable1; /* 0x60 - Interrupt Enable 1 */
  25. u32 interrupt_enable2; /* 0x64 - Interrupt Enable 2 */
  26. u32 interrupt_enable3; /* 0x68 - Interrupt Enable 3 */
  27. };
  28. struct cadence_ttc_priv {
  29. struct cadence_ttc_regs *regs;
  30. };
  31. #if CONFIG_IS_ENABLED(BOOTSTAGE)
  32. ulong timer_get_boot_us(void)
  33. {
  34. u64 ticks = 0;
  35. u32 rate = 1;
  36. u64 us;
  37. int ret;
  38. ret = dm_timer_init();
  39. if (!ret) {
  40. /* The timer is available */
  41. rate = timer_get_rate(gd->timer);
  42. timer_get_count(gd->timer, &ticks);
  43. } else {
  44. return 0;
  45. }
  46. us = (ticks * 1000) / rate;
  47. return us;
  48. }
  49. #endif
  50. static int cadence_ttc_get_count(struct udevice *dev, u64 *count)
  51. {
  52. struct cadence_ttc_priv *priv = dev_get_priv(dev);
  53. *count = readl(&priv->regs->counter_val1);
  54. return 0;
  55. }
  56. static int cadence_ttc_probe(struct udevice *dev)
  57. {
  58. struct cadence_ttc_priv *priv = dev_get_priv(dev);
  59. /* Disable interrupts for sure */
  60. writel(0, &priv->regs->interrupt_enable1);
  61. writel(0, &priv->regs->interrupt_enable2);
  62. writel(0, &priv->regs->interrupt_enable3);
  63. /* Make sure that clocks are configured properly without prescaller */
  64. writel(0, &priv->regs->clk_cntrl1);
  65. writel(0, &priv->regs->clk_cntrl2);
  66. writel(0, &priv->regs->clk_cntrl3);
  67. /* Reset and enable this counter */
  68. writel(CNT_CNTRL_RESET, &priv->regs->counter_cntrl1);
  69. return 0;
  70. }
  71. static int cadence_ttc_ofdata_to_platdata(struct udevice *dev)
  72. {
  73. struct cadence_ttc_priv *priv = dev_get_priv(dev);
  74. priv->regs = map_physmem(dev_read_addr(dev),
  75. sizeof(struct cadence_ttc_regs), MAP_NOCACHE);
  76. if (IS_ERR(priv->regs))
  77. return PTR_ERR(priv->regs);
  78. return 0;
  79. }
  80. static const struct timer_ops cadence_ttc_ops = {
  81. .get_count = cadence_ttc_get_count,
  82. };
  83. static const struct udevice_id cadence_ttc_ids[] = {
  84. { .compatible = "cdns,ttc" },
  85. {}
  86. };
  87. U_BOOT_DRIVER(cadence_ttc) = {
  88. .name = "cadence_ttc",
  89. .id = UCLASS_TIMER,
  90. .of_match = cadence_ttc_ids,
  91. .ofdata_to_platdata = cadence_ttc_ofdata_to_platdata,
  92. .priv_auto_alloc_size = sizeof(struct cadence_ttc_priv),
  93. .probe = cadence_ttc_probe,
  94. .ops = &cadence_ttc_ops,
  95. };