stv0991.c 2.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
  4. * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  5. */
  6. #include <common.h>
  7. #include <bootstage.h>
  8. #include <dm.h>
  9. #include <miiphy.h>
  10. #include <net.h>
  11. #include <asm/arch/stv0991_periph.h>
  12. #include <asm/arch/stv0991_defs.h>
  13. #include <asm/arch/hardware.h>
  14. #include <asm/arch/gpio.h>
  15. #include <netdev.h>
  16. #include <asm/io.h>
  17. #include <dm/platform_data/serial_pl01x.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. struct gpio_regs *const gpioa_regs =
  20. (struct gpio_regs *) GPIOA_BASE_ADDR;
  21. #ifndef CONFIG_OF_CONTROL
  22. static const struct pl01x_serial_platdata serial_platdata = {
  23. .base = 0x80406000,
  24. .type = TYPE_PL011,
  25. .clock = 2700 * 1000,
  26. };
  27. U_BOOT_DEVICE(stv09911_serials) = {
  28. .name = "serial_pl01x",
  29. .platdata = &serial_platdata,
  30. };
  31. #endif
  32. #ifdef CONFIG_SHOW_BOOT_PROGRESS
  33. void show_boot_progress(int progress)
  34. {
  35. printf("%i\n", progress);
  36. }
  37. #endif
  38. void enable_eth_phy(void)
  39. {
  40. /* Set GPIOA_06 pad HIGH (Appli board)*/
  41. writel(readl(&gpioa_regs->dir) | 0x40, &gpioa_regs->dir);
  42. writel(readl(&gpioa_regs->data) | 0x40, &gpioa_regs->data);
  43. }
  44. int board_eth_enable(void)
  45. {
  46. stv0991_pinmux_config(ETH_GPIOB_10_31_C_0_4);
  47. clock_setup(ETH_CLOCK_CFG);
  48. enable_eth_phy();
  49. return 0;
  50. }
  51. int board_qspi_enable(void)
  52. {
  53. stv0991_pinmux_config(QSPI_CS_CLK_PAD);
  54. clock_setup(QSPI_CLOCK_CFG);
  55. return 0;
  56. }
  57. /*
  58. * Miscellaneous platform dependent initialisations
  59. */
  60. int board_init(void)
  61. {
  62. board_eth_enable();
  63. board_qspi_enable();
  64. return 0;
  65. }
  66. int board_uart_init(void)
  67. {
  68. stv0991_pinmux_config(UART_GPIOC_30_31);
  69. clock_setup(UART_CLOCK_CFG);
  70. return 0;
  71. }
  72. #ifdef CONFIG_BOARD_EARLY_INIT_F
  73. int board_early_init_f(void)
  74. {
  75. board_uart_init();
  76. return 0;
  77. }
  78. #endif
  79. int dram_init(void)
  80. {
  81. gd->ram_size = PHYS_SDRAM_1_SIZE;
  82. return 0;
  83. }
  84. int dram_init_banksize(void)
  85. {
  86. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  87. gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  88. return 0;
  89. }
  90. #ifdef CONFIG_CMD_NET
  91. int board_eth_init(bd_t *bis)
  92. {
  93. int ret = 0;
  94. #if defined(CONFIG_ETH_DESIGNWARE)
  95. u32 interface = PHY_INTERFACE_MODE_MII;
  96. if (designware_initialize(GMAC_BASE_ADDR, interface) >= 0)
  97. ret++;
  98. #endif
  99. return ret;
  100. }
  101. #endif