board.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * (C) Copyright 2016
  6. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  7. *
  8. * Based on:
  9. * Board functions for TI AM335X based boards
  10. *
  11. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  12. */
  13. #include <common.h>
  14. #include <bootstage.h>
  15. #include <cpu_func.h>
  16. #include <env.h>
  17. #include <errno.h>
  18. #include <init.h>
  19. #include <irq_func.h>
  20. #include <net.h>
  21. #include <spl.h>
  22. #include <asm/arch/cpu.h>
  23. #include <asm/arch/hardware.h>
  24. #include <asm/arch/omap.h>
  25. #include <asm/arch/ddr_defs.h>
  26. #include <asm/arch/clock.h>
  27. #include <asm/arch/gpio.h>
  28. #include <asm/arch/mmc_host_def.h>
  29. #include <asm/arch/sys_proto.h>
  30. #include <asm/arch/mem.h>
  31. #include <asm/io.h>
  32. #include <asm/emif.h>
  33. #include <asm/gpio.h>
  34. #include <i2c.h>
  35. #include <miiphy.h>
  36. #include <cpsw.h>
  37. #include <power/tps65217.h>
  38. #include <env_internal.h>
  39. #include <watchdog.h>
  40. #include "mmc.h"
  41. #include "board.h"
  42. DECLARE_GLOBAL_DATA_PTR;
  43. static struct shc_eeprom __attribute__((section(".data"))) header;
  44. static int shc_eeprom_valid;
  45. /*
  46. * Read header information from EEPROM into global structure.
  47. */
  48. static int read_eeprom(void)
  49. {
  50. /* Check if baseboard eeprom is available */
  51. if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
  52. puts("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
  53. return -ENODEV;
  54. }
  55. /* read the eeprom using i2c */
  56. if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
  57. sizeof(header))) {
  58. puts("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n");
  59. return -EIO;
  60. }
  61. if (header.magic != HDR_MAGIC) {
  62. printf("Incorrect magic number (0x%x) in EEPROM\n",
  63. header.magic);
  64. return -EIO;
  65. }
  66. shc_eeprom_valid = 1;
  67. return 0;
  68. }
  69. static void shc_request_gpio(void)
  70. {
  71. gpio_request(LED_PWR_BL_GPIO, "LED PWR BL");
  72. gpio_request(LED_PWR_RD_GPIO, "LED PWR RD");
  73. gpio_request(RESET_GPIO, "reset");
  74. gpio_request(WIFI_REGEN_GPIO, "WIFI REGEN");
  75. gpio_request(WIFI_RST_GPIO, "WIFI rst");
  76. gpio_request(ZIGBEE_RST_GPIO, "ZigBee rst");
  77. gpio_request(BIDCOS_RST_GPIO, "BIDCOS rst");
  78. gpio_request(ENOC_RST_GPIO, "ENOC rst");
  79. #if defined CONFIG_B_SAMPLE
  80. gpio_request(LED_PWR_GN_GPIO, "LED PWR GN");
  81. gpio_request(LED_CONN_BL_GPIO, "LED CONN BL");
  82. gpio_request(LED_CONN_RD_GPIO, "LED CONN RD");
  83. gpio_request(LED_CONN_GN_GPIO, "LED CONN GN");
  84. #else
  85. gpio_request(LED_LAN_BL_GPIO, "LED LAN BL");
  86. gpio_request(LED_LAN_RD_GPIO, "LED LAN RD");
  87. gpio_request(LED_CLOUD_BL_GPIO, "LED CLOUD BL");
  88. gpio_request(LED_CLOUD_RD_GPIO, "LED CLOUD RD");
  89. gpio_request(LED_PWM_GPIO, "LED PWM");
  90. gpio_request(Z_WAVE_RST_GPIO, "Z WAVE rst");
  91. #endif
  92. gpio_request(BACK_BUTTON_GPIO, "Back button");
  93. gpio_request(FRONT_BUTTON_GPIO, "Front button");
  94. }
  95. /*
  96. * Function which forces all installed modules into running state for ICT
  97. * testing. Called by SPL.
  98. */
  99. static void __maybe_unused force_modules_running(void)
  100. {
  101. /* Wi-Fi power regulator enable - high = enabled */
  102. gpio_direction_output(WIFI_REGEN_GPIO, 1);
  103. /*
  104. * Wait for Wi-Fi power regulator to reach a stable voltage
  105. * (soft-start time, max. 350 µs)
  106. */
  107. __udelay(350);
  108. /* Wi-Fi module reset - high = running */
  109. gpio_direction_output(WIFI_RST_GPIO, 1);
  110. /* ZigBee reset - high = running */
  111. gpio_direction_output(ZIGBEE_RST_GPIO, 1);
  112. /* BidCos reset - high = running */
  113. gpio_direction_output(BIDCOS_RST_GPIO, 1);
  114. #if !defined(CONFIG_B_SAMPLE)
  115. /* Z-Wave reset - high = running */
  116. gpio_direction_output(Z_WAVE_RST_GPIO, 1);
  117. #endif
  118. /* EnOcean reset - low = running */
  119. gpio_direction_output(ENOC_RST_GPIO, 0);
  120. }
  121. /*
  122. * Function which forces all installed modules into reset - to be released by
  123. * the OS, called by SPL
  124. */
  125. static void __maybe_unused force_modules_reset(void)
  126. {
  127. /* Wi-Fi module reset - low = reset */
  128. gpio_direction_output(WIFI_RST_GPIO, 0);
  129. /* Wi-Fi power regulator enable - low = disabled */
  130. gpio_direction_output(WIFI_REGEN_GPIO, 0);
  131. /* ZigBee reset - low = reset */
  132. gpio_direction_output(ZIGBEE_RST_GPIO, 0);
  133. /* BidCos reset - low = reset */
  134. /*gpio_direction_output(BIDCOS_RST_GPIO, 0);*/
  135. #if !defined(CONFIG_B_SAMPLE)
  136. /* Z-Wave reset - low = reset */
  137. gpio_direction_output(Z_WAVE_RST_GPIO, 0);
  138. #endif
  139. /* EnOcean reset - high = reset*/
  140. gpio_direction_output(ENOC_RST_GPIO, 1);
  141. }
  142. /*
  143. * Function to set the LEDs in the state "Bootloader booting"
  144. */
  145. static void __maybe_unused leds_set_booting(void)
  146. {
  147. #if defined(CONFIG_B_SAMPLE)
  148. /* Turn all red LEDs on */
  149. gpio_direction_output(LED_PWR_RD_GPIO, 1);
  150. gpio_direction_output(LED_CONN_RD_GPIO, 1);
  151. #else /* All other SHCs starting with B2-Sample */
  152. /* Set the PWM GPIO */
  153. gpio_direction_output(LED_PWM_GPIO, 1);
  154. /* Turn all red LEDs on */
  155. gpio_direction_output(LED_PWR_RD_GPIO, 1);
  156. gpio_direction_output(LED_LAN_RD_GPIO, 1);
  157. gpio_direction_output(LED_CLOUD_RD_GPIO, 1);
  158. #endif
  159. }
  160. /*
  161. * Function to set the LEDs in the state "Bootloader error"
  162. */
  163. static void leds_set_failure(int state)
  164. {
  165. #if defined(CONFIG_B_SAMPLE)
  166. /* Turn all blue and green LEDs off */
  167. gpio_set_value(LED_PWR_BL_GPIO, 0);
  168. gpio_set_value(LED_PWR_GN_GPIO, 0);
  169. gpio_set_value(LED_CONN_BL_GPIO, 0);
  170. gpio_set_value(LED_CONN_GN_GPIO, 0);
  171. /* Turn all red LEDs to 'state' */
  172. gpio_set_value(LED_PWR_RD_GPIO, state);
  173. gpio_set_value(LED_CONN_RD_GPIO, state);
  174. #else /* All other SHCs starting with B2-Sample */
  175. /* Set the PWM GPIO */
  176. gpio_direction_output(LED_PWM_GPIO, 1);
  177. /* Turn all blue LEDs off */
  178. gpio_set_value(LED_PWR_BL_GPIO, 0);
  179. gpio_set_value(LED_LAN_BL_GPIO, 0);
  180. gpio_set_value(LED_CLOUD_BL_GPIO, 0);
  181. /* Turn all red LEDs to 'state' */
  182. gpio_set_value(LED_PWR_RD_GPIO, state);
  183. gpio_set_value(LED_LAN_RD_GPIO, state);
  184. gpio_set_value(LED_CLOUD_RD_GPIO, state);
  185. #endif
  186. }
  187. /*
  188. * Function to set the LEDs in the state "Bootloader finished"
  189. */
  190. static void leds_set_finish(void)
  191. {
  192. #if defined(CONFIG_B_SAMPLE)
  193. /* Turn all LEDs off */
  194. gpio_set_value(LED_PWR_BL_GPIO, 0);
  195. gpio_set_value(LED_PWR_RD_GPIO, 0);
  196. gpio_set_value(LED_PWR_GN_GPIO, 0);
  197. gpio_set_value(LED_CONN_BL_GPIO, 0);
  198. gpio_set_value(LED_CONN_RD_GPIO, 0);
  199. gpio_set_value(LED_CONN_GN_GPIO, 0);
  200. #else /* All other SHCs starting with B2-Sample */
  201. /* Turn all LEDs off */
  202. gpio_set_value(LED_PWR_BL_GPIO, 0);
  203. gpio_set_value(LED_PWR_RD_GPIO, 0);
  204. gpio_set_value(LED_LAN_BL_GPIO, 0);
  205. gpio_set_value(LED_LAN_RD_GPIO, 0);
  206. gpio_set_value(LED_CLOUD_BL_GPIO, 0);
  207. gpio_set_value(LED_CLOUD_RD_GPIO, 0);
  208. /* Turn off the PWM GPIO and mux it to EHRPWM */
  209. gpio_set_value(LED_PWM_GPIO, 0);
  210. enable_shc_board_pwm_pin_mux();
  211. #endif
  212. }
  213. static void check_button_status(void)
  214. {
  215. ulong value;
  216. gpio_direction_input(FRONT_BUTTON_GPIO);
  217. value = gpio_get_value(FRONT_BUTTON_GPIO);
  218. if (value == 0) {
  219. printf("front button activated !\n");
  220. env_set("harakiri", "1");
  221. }
  222. }
  223. #if defined(CONFIG_SPL_BUILD)
  224. #ifdef CONFIG_SPL_OS_BOOT
  225. int spl_start_uboot(void)
  226. {
  227. return 1;
  228. }
  229. #endif
  230. static void shc_board_early_init(void)
  231. {
  232. shc_request_gpio();
  233. # ifdef CONFIG_SHC_ICT
  234. /* Force all modules into enabled state for ICT testing */
  235. force_modules_running();
  236. # else
  237. /* Force all modules to enter Reset state until released by the OS */
  238. force_modules_reset();
  239. # endif
  240. leds_set_booting();
  241. }
  242. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  243. #define MPU_SPREADING_PERMILLE 18 /* Spread 1.8 percent */
  244. #define OSC (V_OSCK/1000000)
  245. /* Bosch: Predivider must be fixed to 4, so N = 4-1 */
  246. #define MPUPLL_N (4-1)
  247. /* Bosch: Fref = 24 MHz / (N+1) = 24 MHz / 4 = 6 MHz */
  248. #define MPUPLL_FREF (OSC / (MPUPLL_N + 1))
  249. const struct dpll_params dpll_ddr_shc = {
  250. 400, OSC-1, 1, -1, -1, -1, -1};
  251. const struct dpll_params *get_dpll_ddr_params(void)
  252. {
  253. return &dpll_ddr_shc;
  254. }
  255. /*
  256. * As we enabled downspread SSC with 1.8%, the values needed to be corrected
  257. * such that the 20% overshoot will not lead to too high frequencies.
  258. * In all cases, this is achieved by subtracting one from M (6 MHz less).
  259. * Example: 600 MHz CPU
  260. * Step size: 24 MHz OSC, N = 4 (fix) --> Fref = 6 MHz
  261. * 600 MHz - 6 MHz (1x Fref) = 594 MHz
  262. * SSC: 594 MHz * 1.8% = 10.7 MHz SSC
  263. * Overshoot: 10.7 MHz * 20 % = 2.2 MHz
  264. * --> Fmax = 594 MHz + 2.2 MHz = 596.2 MHz, lower than 600 MHz --> OK!
  265. */
  266. const struct dpll_params dpll_mpu_shc_opp100 = {
  267. 99, MPUPLL_N, 1, -1, -1, -1, -1};
  268. void am33xx_spl_board_init(void)
  269. {
  270. int sil_rev;
  271. int mpu_vdd;
  272. puts(BOARD_ID_STR);
  273. /*
  274. * Set CORE Frequency to OPP100
  275. * Hint: DCDC3 (CORE) defaults to 1.100V (for OPP100)
  276. */
  277. do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
  278. sil_rev = readl(&cdev->deviceid) >> 28;
  279. if (sil_rev < 2) {
  280. puts("We do not support Silicon Revisions below 2.0!\n");
  281. return;
  282. }
  283. dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
  284. if (i2c_probe(TPS65217_CHIP_PM))
  285. return;
  286. /*
  287. * Retrieve the CPU max frequency by reading the efuse
  288. * SHC-Default: 600 MHz
  289. */
  290. switch (dpll_mpu_opp100.m) {
  291. case MPUPLL_M_1000:
  292. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
  293. break;
  294. case MPUPLL_M_800:
  295. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
  296. break;
  297. case MPUPLL_M_720:
  298. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
  299. break;
  300. case MPUPLL_M_600:
  301. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
  302. break;
  303. case MPUPLL_M_300:
  304. mpu_vdd = TPS65217_DCDC_VOLT_SEL_950MV;
  305. break;
  306. default:
  307. puts("Cannot determine the frequency, failing!\n");
  308. return;
  309. }
  310. if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
  311. puts("tps65217_voltage_update failure\n");
  312. return;
  313. }
  314. /* Set MPU Frequency to what we detected */
  315. printf("MPU reference clock runs at %d MHz\n", MPUPLL_FREF);
  316. printf("Setting MPU clock to %d MHz\n", MPUPLL_FREF *
  317. dpll_mpu_shc_opp100.m);
  318. do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_shc_opp100);
  319. /* Enable Spread Spectrum for this freq to be clean on EMI side */
  320. set_mpu_spreadspectrum(MPU_SPREADING_PERMILLE);
  321. /*
  322. * Using the default voltages for the PMIC (TPS65217D)
  323. * LS1 = 1.8V (VDD_1V8)
  324. * LS2 = 3.3V (VDD_3V3A)
  325. * LDO1 = 1.8V (VIO and VRTC)
  326. * LDO2 = 3.3V (VDD_3V3AUX)
  327. */
  328. shc_board_early_init();
  329. }
  330. void set_uart_mux_conf(void)
  331. {
  332. enable_uart0_pin_mux();
  333. }
  334. void set_mux_conf_regs(void)
  335. {
  336. enable_shc_board_pin_mux();
  337. }
  338. const struct ctrl_ioregs ioregs_evmsk = {
  339. .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  340. .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  341. .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  342. .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  343. .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  344. };
  345. static const struct ddr_data ddr3_shc_data = {
  346. .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  347. .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  348. .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  349. .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  350. };
  351. static const struct cmd_control ddr3_shc_cmd_ctrl_data = {
  352. .cmd0csratio = MT41K256M16HA125E_RATIO,
  353. .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  354. .cmd1csratio = MT41K256M16HA125E_RATIO,
  355. .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  356. .cmd2csratio = MT41K256M16HA125E_RATIO,
  357. .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  358. };
  359. static struct emif_regs ddr3_shc_emif_reg_data = {
  360. .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  361. .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  362. .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  363. .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  364. .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  365. .zq_config = MT41K256M16HA125E_ZQ_CFG,
  366. .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
  367. PHY_EN_DYN_PWRDN,
  368. };
  369. void sdram_init(void)
  370. {
  371. /* Configure the DDR3 RAM */
  372. config_ddr(400, &ioregs_evmsk, &ddr3_shc_data,
  373. &ddr3_shc_cmd_ctrl_data, &ddr3_shc_emif_reg_data, 0);
  374. }
  375. #endif
  376. /*
  377. * Basic board specific setup. Pinmux has been handled already.
  378. */
  379. int board_init(void)
  380. {
  381. #if defined(CONFIG_HW_WATCHDOG)
  382. hw_watchdog_init();
  383. #endif
  384. i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  385. if (read_eeprom() < 0)
  386. puts("EEPROM Content Invalid.\n");
  387. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  388. #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
  389. gpmc_init();
  390. #endif
  391. shc_request_gpio();
  392. return 0;
  393. }
  394. #ifdef CONFIG_BOARD_LATE_INIT
  395. int board_late_init(void)
  396. {
  397. check_button_status();
  398. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  399. if (shc_eeprom_valid)
  400. if (is_valid_ethaddr(header.mac_addr))
  401. eth_env_set_enetaddr("ethaddr", header.mac_addr);
  402. #endif
  403. return 0;
  404. }
  405. #endif
  406. #if defined(CONFIG_USB_ETHER) && \
  407. (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER))
  408. int board_eth_init(bd_t *bis)
  409. {
  410. return usb_eth_initialize(bis);
  411. }
  412. #endif
  413. #ifdef CONFIG_SHOW_BOOT_PROGRESS
  414. static void bosch_check_reset_pin(void)
  415. {
  416. if (readl(GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0) & RESET_MASK) {
  417. printf("Resetting ...\n");
  418. writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0);
  419. disable_interrupts();
  420. reset_cpu(0);
  421. /*NOTREACHED*/
  422. }
  423. }
  424. static void hang_bosch(const char *cause, int code)
  425. {
  426. int lv;
  427. gpio_direction_input(RESET_GPIO);
  428. /* Enable reset pin interrupt on falling edge */
  429. writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0);
  430. writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_FALLINGDETECT);
  431. enable_interrupts();
  432. puts(cause);
  433. for (;;) {
  434. for (lv = 0; lv < code; lv++) {
  435. bosch_check_reset_pin();
  436. leds_set_failure(1);
  437. __udelay(150 * 1000);
  438. leds_set_failure(0);
  439. __udelay(150 * 1000);
  440. }
  441. #if defined(BLINK_CODE)
  442. __udelay(300 * 1000);
  443. #endif
  444. }
  445. }
  446. void show_boot_progress(int val)
  447. {
  448. switch (val) {
  449. case BOOTSTAGE_ID_NEED_RESET:
  450. hang_bosch("need reset", 4);
  451. break;
  452. }
  453. }
  454. void arch_preboot_os(void)
  455. {
  456. leds_set_finish();
  457. }
  458. #endif