fsp_silicon_init.c 1.5 KB

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  1. // SPDX-License-Identifier: Intel
  2. /*
  3. * Copyright (C) 2015-2016 Intel Corp.
  4. * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
  5. *
  6. * Mostly taken from coreboot fsp2_0/silicon_init.c
  7. */
  8. #define LOG_CATEGORY UCLASS_NORTHBRIDGE
  9. #include <common.h>
  10. #include <binman.h>
  11. #include <bootstage.h>
  12. #include <dm.h>
  13. #include <asm/arch/fsp/fsp_configs.h>
  14. #include <asm/arch/fsp/fsp_s_upd.h>
  15. #include <asm/fsp/fsp_infoheader.h>
  16. #include <asm/fsp2/fsp_internal.h>
  17. int fsp_silicon_init(bool s3wake, bool use_spi_flash)
  18. {
  19. struct fsps_upd upd, *fsp_upd;
  20. fsp_silicon_init_func func;
  21. struct fsp_header *hdr;
  22. struct binman_entry entry;
  23. struct udevice *dev;
  24. ulong rom_offset = 0;
  25. int ret;
  26. ret = fsp_locate_fsp(FSP_S, &entry, use_spi_flash, &dev, &hdr,
  27. &rom_offset);
  28. if (ret)
  29. return log_msg_ret("locate FSP", ret);
  30. gd->arch.fsp_s_hdr = hdr;
  31. /* Copy over the default config */
  32. fsp_upd = (struct fsps_upd *)(hdr->img_base + hdr->cfg_region_off);
  33. if (fsp_upd->header.signature != FSPS_UPD_SIGNATURE)
  34. return log_msg_ret("Bad UPD signature", -EPERM);
  35. memcpy(&upd, fsp_upd, sizeof(upd));
  36. ret = fsps_update_config(dev, rom_offset, &upd);
  37. if (ret)
  38. return log_msg_ret("Could not setup config", ret);
  39. log_debug("Silicon init...");
  40. bootstage_start(BOOTSTAGE_ID_ACCUM_FSP_S, "fsp-s");
  41. func = (fsp_silicon_init_func)(hdr->img_base + hdr->fsp_silicon_init);
  42. ret = func(&upd);
  43. bootstage_accum(BOOTSTAGE_ID_ACCUM_FSP_S);
  44. if (ret)
  45. return log_msg_ret("Silicon init fail\n", ret);
  46. log_debug("done\n");
  47. return 0;
  48. }