cpu.c 6.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2008-2011
  4. * Graeme Russ, <graeme.russ@gmail.com>
  5. *
  6. * (C) Copyright 2002
  7. * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
  8. *
  9. * (C) Copyright 2002
  10. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  11. * Marius Groeger <mgroeger@sysgo.de>
  12. *
  13. * (C) Copyright 2002
  14. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  15. * Alex Zuepke <azu@sysgo.de>
  16. *
  17. * Part of this file is adapted from coreboot
  18. * src/arch/x86/lib/cpu.c
  19. */
  20. #include <common.h>
  21. #include <bootstage.h>
  22. #include <command.h>
  23. #include <cpu_func.h>
  24. #include <dm.h>
  25. #include <errno.h>
  26. #include <init.h>
  27. #include <malloc.h>
  28. #include <syscon.h>
  29. #include <acpi/acpi_s3.h>
  30. #include <acpi/acpi_table.h>
  31. #include <asm/acpi.h>
  32. #include <asm/control_regs.h>
  33. #include <asm/coreboot_tables.h>
  34. #include <asm/cpu.h>
  35. #include <asm/lapic.h>
  36. #include <asm/microcode.h>
  37. #include <asm/mp.h>
  38. #include <asm/mrccache.h>
  39. #include <asm/msr.h>
  40. #include <asm/mtrr.h>
  41. #include <asm/post.h>
  42. #include <asm/processor.h>
  43. #include <asm/processor-flags.h>
  44. #include <asm/interrupt.h>
  45. #include <asm/tables.h>
  46. #include <linux/compiler.h>
  47. DECLARE_GLOBAL_DATA_PTR;
  48. #ifndef CONFIG_TPL_BUILD
  49. static const char *const x86_vendor_name[] = {
  50. [X86_VENDOR_INTEL] = "Intel",
  51. [X86_VENDOR_CYRIX] = "Cyrix",
  52. [X86_VENDOR_AMD] = "AMD",
  53. [X86_VENDOR_UMC] = "UMC",
  54. [X86_VENDOR_NEXGEN] = "NexGen",
  55. [X86_VENDOR_CENTAUR] = "Centaur",
  56. [X86_VENDOR_RISE] = "Rise",
  57. [X86_VENDOR_TRANSMETA] = "Transmeta",
  58. [X86_VENDOR_NSC] = "NSC",
  59. [X86_VENDOR_SIS] = "SiS",
  60. };
  61. #endif
  62. int __weak x86_cleanup_before_linux(void)
  63. {
  64. #ifdef CONFIG_BOOTSTAGE_STASH
  65. bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR,
  66. CONFIG_BOOTSTAGE_STASH_SIZE);
  67. #endif
  68. return 0;
  69. }
  70. int x86_init_cache(void)
  71. {
  72. enable_caches();
  73. return 0;
  74. }
  75. int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
  76. void flush_cache(unsigned long dummy1, unsigned long dummy2)
  77. {
  78. asm("wbinvd\n");
  79. }
  80. /* Define these functions to allow ehch-hcd to function */
  81. void flush_dcache_range(unsigned long start, unsigned long stop)
  82. {
  83. }
  84. void invalidate_dcache_range(unsigned long start, unsigned long stop)
  85. {
  86. }
  87. void dcache_enable(void)
  88. {
  89. enable_caches();
  90. }
  91. void dcache_disable(void)
  92. {
  93. disable_caches();
  94. }
  95. void icache_enable(void)
  96. {
  97. }
  98. void icache_disable(void)
  99. {
  100. }
  101. int icache_status(void)
  102. {
  103. return 1;
  104. }
  105. #ifndef CONFIG_TPL_BUILD
  106. const char *cpu_vendor_name(int vendor)
  107. {
  108. const char *name;
  109. name = "<invalid cpu vendor>";
  110. if (vendor < ARRAY_SIZE(x86_vendor_name) &&
  111. x86_vendor_name[vendor])
  112. name = x86_vendor_name[vendor];
  113. return name;
  114. }
  115. #endif
  116. char *cpu_get_name(char *name)
  117. {
  118. unsigned int *name_as_ints = (unsigned int *)name;
  119. struct cpuid_result regs;
  120. char *ptr;
  121. int i;
  122. /* This bit adds up to 48 bytes */
  123. for (i = 0; i < 3; i++) {
  124. regs = cpuid(0x80000002 + i);
  125. name_as_ints[i * 4 + 0] = regs.eax;
  126. name_as_ints[i * 4 + 1] = regs.ebx;
  127. name_as_ints[i * 4 + 2] = regs.ecx;
  128. name_as_ints[i * 4 + 3] = regs.edx;
  129. }
  130. name[CPU_MAX_NAME_LEN - 1] = '\0';
  131. /* Skip leading spaces. */
  132. ptr = name;
  133. while (*ptr == ' ')
  134. ptr++;
  135. return ptr;
  136. }
  137. int default_print_cpuinfo(void)
  138. {
  139. printf("CPU: %s, vendor %s, device %xh\n",
  140. cpu_has_64bit() ? "x86_64" : "x86",
  141. cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device);
  142. #ifdef CONFIG_HAVE_ACPI_RESUME
  143. debug("ACPI previous sleep state: %s\n",
  144. acpi_ss_string(gd->arch.prev_sleep_state));
  145. #endif
  146. return 0;
  147. }
  148. void show_boot_progress(int val)
  149. {
  150. outb(val, POST_PORT);
  151. }
  152. #if !defined(CONFIG_SYS_COREBOOT) && !defined(CONFIG_EFI_STUB)
  153. /*
  154. * Implement a weak default function for boards that optionally
  155. * need to clean up the system before jumping to the kernel.
  156. */
  157. __weak void board_final_cleanup(void)
  158. {
  159. }
  160. int last_stage_init(void)
  161. {
  162. struct acpi_fadt __maybe_unused *fadt;
  163. board_final_cleanup();
  164. #ifdef CONFIG_HAVE_ACPI_RESUME
  165. fadt = acpi_find_fadt();
  166. if (fadt && gd->arch.prev_sleep_state == ACPI_S3)
  167. acpi_resume(fadt);
  168. #endif
  169. write_tables();
  170. #ifdef CONFIG_GENERATE_ACPI_TABLE
  171. fadt = acpi_find_fadt();
  172. /* Don't touch ACPI hardware on HW reduced platforms */
  173. if (fadt && !(fadt->flags & ACPI_FADT_HW_REDUCED_ACPI)) {
  174. /*
  175. * Other than waiting for OSPM to request us to switch to ACPI
  176. * mode, do it by ourselves, since SMI will not be triggered.
  177. */
  178. enter_acpi_mode(fadt->pm1a_cnt_blk);
  179. }
  180. #endif
  181. return 0;
  182. }
  183. #endif
  184. static int x86_init_cpus(void)
  185. {
  186. #ifdef CONFIG_SMP
  187. debug("Init additional CPUs\n");
  188. x86_mp_init();
  189. #else
  190. struct udevice *dev;
  191. /*
  192. * This causes the cpu-x86 driver to be probed.
  193. * We don't check return value here as we want to allow boards
  194. * which have not been converted to use cpu uclass driver to boot.
  195. */
  196. uclass_first_device(UCLASS_CPU, &dev);
  197. #endif
  198. return 0;
  199. }
  200. int cpu_init_r(void)
  201. {
  202. struct udevice *dev;
  203. int ret;
  204. if (!ll_boot_init()) {
  205. uclass_first_device(UCLASS_PCI, &dev);
  206. return 0;
  207. }
  208. ret = x86_init_cpus();
  209. if (ret)
  210. return ret;
  211. /*
  212. * Set up the northbridge, PCH and LPC if available. Note that these
  213. * may have had some limited pre-relocation init if they were probed
  214. * before relocation, but this is post relocation.
  215. */
  216. uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
  217. uclass_first_device(UCLASS_PCH, &dev);
  218. uclass_first_device(UCLASS_LPC, &dev);
  219. /* Set up pin control if available */
  220. ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
  221. debug("%s, pinctrl=%p, ret=%d\n", __func__, dev, ret);
  222. return 0;
  223. }
  224. #ifndef CONFIG_EFI_STUB
  225. int reserve_arch(void)
  226. {
  227. #ifdef CONFIG_ENABLE_MRC_CACHE
  228. mrccache_reserve();
  229. #endif
  230. #ifdef CONFIG_SEABIOS
  231. high_table_reserve();
  232. #endif
  233. #ifdef CONFIG_HAVE_ACPI_RESUME
  234. acpi_s3_reserve();
  235. #ifdef CONFIG_HAVE_FSP
  236. /*
  237. * Save stack address to CMOS so that at next S3 boot,
  238. * we can use it as the stack address for fsp_contiue()
  239. */
  240. fsp_save_s3_stack();
  241. #endif /* CONFIG_HAVE_FSP */
  242. #endif /* CONFIG_HAVE_ACPI_RESUME */
  243. return 0;
  244. }
  245. #endif
  246. long detect_coreboot_table_at(ulong start, ulong size)
  247. {
  248. u32 *ptr, *end;
  249. size /= 4;
  250. for (ptr = (void *)start, end = ptr + size; ptr < end; ptr += 4) {
  251. if (*ptr == 0x4f49424c) /* "LBIO" */
  252. return (long)ptr;
  253. }
  254. return -ENOENT;
  255. }
  256. long locate_coreboot_table(void)
  257. {
  258. long addr;
  259. /* We look for LBIO in the first 4K of RAM and again at 960KB */
  260. addr = detect_coreboot_table_at(0x0, 0x1000);
  261. if (addr < 0)
  262. addr = detect_coreboot_table_at(0xf0000, 0x1000);
  263. return addr;
  264. }