spl.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2019 Google LLC
  4. */
  5. #include <common.h>
  6. #include <binman_sym.h>
  7. #include <bootstage.h>
  8. #include <dm.h>
  9. #include <malloc.h>
  10. #include <spi.h>
  11. #include <spl.h>
  12. #include <spi_flash.h>
  13. #include <asm/fast_spi.h>
  14. #include <asm/spl.h>
  15. #include <asm/arch/cpu.h>
  16. #include <asm/arch/iomap.h>
  17. #include <dm/device-internal.h>
  18. #include <dm/uclass-internal.h>
  19. /* This reads the next phase from mapped SPI flash */
  20. static int rom_load_image(struct spl_image_info *spl_image,
  21. struct spl_boot_device *bootdev)
  22. {
  23. ulong spl_pos = spl_get_image_pos();
  24. ulong spl_size = spl_get_image_size();
  25. struct udevice *dev;
  26. ulong map_base;
  27. size_t map_size;
  28. uint offset;
  29. int ret;
  30. spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */
  31. spl_image->entry_point = spl_phase() == PHASE_TPL ?
  32. CONFIG_SPL_TEXT_BASE : CONFIG_SYS_TEXT_BASE;
  33. spl_image->load_addr = spl_image->entry_point;
  34. spl_image->os = IH_OS_U_BOOT;
  35. spl_image->name = "U-Boot";
  36. debug("Reading from mapped SPI %lx, size %lx", spl_pos, spl_size);
  37. if (CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)) {
  38. ret = uclass_find_first_device(UCLASS_SPI_FLASH, &dev);
  39. if (ret)
  40. return log_msg_ret("spi_flash", ret);
  41. if (!dev)
  42. return log_msg_ret("spi_flash dev", -ENODEV);
  43. ret = dm_spi_get_mmap(dev, &map_base, &map_size, &offset);
  44. if (ret)
  45. return log_msg_ret("mmap", ret);
  46. } else {
  47. ret = fast_spi_get_bios_mmap(PCH_DEV_SPI, &map_base, &map_size,
  48. &offset);
  49. if (ret)
  50. return ret;
  51. }
  52. spl_pos += map_base & ~0xff000000;
  53. debug(", base %lx, pos %lx\n", map_base, spl_pos);
  54. bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
  55. memcpy((void *)spl_image->load_addr, (void *)spl_pos, spl_size);
  56. cpu_flush_l1d_to_l2();
  57. bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
  58. return 0;
  59. }
  60. SPL_LOAD_IMAGE_METHOD("Mapped SPI", 2, BOOT_DEVICE_SPI_MMAP, rom_load_image);
  61. #if CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)
  62. static int apl_flash_std_read(struct udevice *dev, u32 offset, size_t len,
  63. void *buf)
  64. {
  65. struct spi_flash *flash = dev_get_uclass_priv(dev);
  66. struct mtd_info *mtd = &flash->mtd;
  67. size_t retlen;
  68. return log_ret(mtd->_read(mtd, offset, len, &retlen, buf));
  69. }
  70. static int apl_flash_probe(struct udevice *dev)
  71. {
  72. return spi_flash_std_probe(dev);
  73. }
  74. /*
  75. * Manually set the parent of the SPI flash to SPI, since dtoc doesn't. We also
  76. * need to allocate the parent_platdata since by the time this function is
  77. * called device_bind() has already gone past that step.
  78. */
  79. static int apl_flash_bind(struct udevice *dev)
  80. {
  81. if (CONFIG_IS_ENABLED(OF_PLATDATA)) {
  82. struct dm_spi_slave_platdata *plat;
  83. struct udevice *spi;
  84. int ret;
  85. ret = uclass_first_device_err(UCLASS_SPI, &spi);
  86. if (ret)
  87. return ret;
  88. dev->parent = spi;
  89. plat = calloc(sizeof(*plat), 1);
  90. if (!plat)
  91. return -ENOMEM;
  92. dev->parent_platdata = plat;
  93. }
  94. return 0;
  95. }
  96. static const struct dm_spi_flash_ops apl_flash_ops = {
  97. .read = apl_flash_std_read,
  98. };
  99. static const struct udevice_id apl_flash_ids[] = {
  100. { .compatible = "jedec,spi-nor" },
  101. { }
  102. };
  103. U_BOOT_DRIVER(winbond_w25q128fw) = {
  104. .name = "winbond_w25q128fw",
  105. .id = UCLASS_SPI_FLASH,
  106. .of_match = apl_flash_ids,
  107. .bind = apl_flash_bind,
  108. .probe = apl_flash_probe,
  109. .priv_auto_alloc_size = sizeof(struct spi_flash),
  110. .ops = &apl_flash_ops,
  111. };
  112. /* This uses a SPI flash device to read the next phase */
  113. static int spl_fast_spi_load_image(struct spl_image_info *spl_image,
  114. struct spl_boot_device *bootdev)
  115. {
  116. ulong spl_pos = spl_get_image_pos();
  117. ulong spl_size = spl_get_image_size();
  118. struct udevice *dev;
  119. int ret;
  120. ret = uclass_first_device_err(UCLASS_SPI_FLASH, &dev);
  121. if (ret)
  122. return ret;
  123. spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */
  124. spl_image->entry_point = spl_phase() == PHASE_TPL ?
  125. CONFIG_SPL_TEXT_BASE : CONFIG_SYS_TEXT_BASE;
  126. spl_image->load_addr = spl_image->entry_point;
  127. spl_image->os = IH_OS_U_BOOT;
  128. spl_image->name = "U-Boot";
  129. spl_pos &= ~0xff000000;
  130. debug("Reading from flash %lx, size %lx\n", spl_pos, spl_size);
  131. ret = spi_flash_read_dm(dev, spl_pos, spl_size,
  132. (void *)spl_image->load_addr);
  133. cpu_flush_l1d_to_l2();
  134. if (ret)
  135. return ret;
  136. return 0;
  137. }
  138. SPL_LOAD_IMAGE_METHOD("Fast SPI", 1, BOOT_DEVICE_FAST_SPI,
  139. spl_fast_spi_load_image);
  140. void board_boot_order(u32 *spl_boot_list)
  141. {
  142. bool use_spi_flash = IS_ENABLED(CONFIG_APL_BOOT_FROM_FAST_SPI_FLASH);
  143. if (use_spi_flash) {
  144. spl_boot_list[0] = BOOT_DEVICE_FAST_SPI;
  145. spl_boot_list[1] = BOOT_DEVICE_SPI_MMAP;
  146. } else {
  147. spl_boot_list[0] = BOOT_DEVICE_SPI_MMAP;
  148. spl_boot_list[1] = BOOT_DEVICE_FAST_SPI;
  149. }
  150. }
  151. #else
  152. void board_boot_order(u32 *spl_boot_list)
  153. {
  154. spl_boot_list[0] = BOOT_DEVICE_SPI_MMAP;
  155. }
  156. #endif