fsp_s.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2019 Google LLC
  4. * Written by Simon Glass <sjg@chromium.org>
  5. */
  6. #include <common.h>
  7. #include <binman.h>
  8. #include <bootstage.h>
  9. #include <dm.h>
  10. #include <irq.h>
  11. #include <malloc.h>
  12. #include <acpi/acpi_s3.h>
  13. #include <asm/intel_pinctrl.h>
  14. #include <asm/io.h>
  15. #include <asm/intel_regs.h>
  16. #include <asm/msr.h>
  17. #include <asm/msr-index.h>
  18. #include <asm/pci.h>
  19. #include <asm/arch/cpu.h>
  20. #include <asm/arch/systemagent.h>
  21. #include <asm/arch/fsp/fsp_configs.h>
  22. #include <asm/arch/fsp/fsp_s_upd.h>
  23. #define PCH_P2SB_E0 0xe0
  24. #define HIDE_BIT BIT(0)
  25. #define INTEL_GSPI_MAX 3
  26. #define MAX_USB2_PORTS 8
  27. enum {
  28. CHIPSET_LOCKDOWN_FSP = 0, /* FSP handles locking per UPDs */
  29. CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */
  30. };
  31. /* Serial IRQ control. SERIRQ_QUIET is the default (0) */
  32. enum serirq_mode {
  33. SERIRQ_QUIET,
  34. SERIRQ_CONTINUOUS,
  35. SERIRQ_OFF,
  36. };
  37. struct gspi_cfg {
  38. /* Bus speed in MHz */
  39. u32 speed_mhz;
  40. /* Bus should be enabled prior to ramstage with temporary base */
  41. u8 early_init;
  42. };
  43. /*
  44. * This structure will hold data required by common blocks.
  45. * These are soc specific configurations which will be filled by soc.
  46. * We'll fill this structure once during init and use the data in common block.
  47. */
  48. struct soc_intel_common_config {
  49. int chipset_lockdown;
  50. struct gspi_cfg gspi[INTEL_GSPI_MAX];
  51. };
  52. enum pnp_settings {
  53. PNP_PERF,
  54. PNP_POWER,
  55. PNP_PERF_POWER,
  56. };
  57. struct usb2_eye_per_port {
  58. u8 per_port_tx_pe_half;
  59. u8 per_port_pe_txi_set;
  60. u8 per_port_txi_set;
  61. u8 hs_skew_sel;
  62. u8 usb_tx_emphasis_en;
  63. u8 per_port_rxi_set;
  64. u8 hs_npre_drv_sel;
  65. u8 override_en;
  66. };
  67. struct apl_config {
  68. /* Common structure containing soc config data required by common code*/
  69. struct soc_intel_common_config common_soc_config;
  70. /*
  71. * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has
  72. * four CLKREQ inputs, but six root ports. Root ports without an
  73. * associated CLKREQ signal must be marked with "CLKREQ_DISABLED"
  74. */
  75. u8 pcie_rp_clkreq_pin[MAX_PCIE_PORTS];
  76. /* Enable/disable hot-plug for root ports (0 = disable, 1 = enable) */
  77. u8 pcie_rp_hotplug_enable[MAX_PCIE_PORTS];
  78. /* De-emphasis enable configuration for each PCIe root port */
  79. u8 pcie_rp_deemphasis_enable[MAX_PCIE_PORTS];
  80. /*
  81. * [14:8] DDR mode Number of dealy elements.Each = 125pSec.
  82. * [6:0] SDR mode Number of dealy elements.Each = 125pSec.
  83. */
  84. u32 emmc_tx_cmd_cntl;
  85. /*
  86. * [14:8] HS400 mode Number of dealy elements.Each = 125pSec.
  87. * [6:0] SDR104/HS200 mode Number of dealy elements.Each = 125pSec.
  88. */
  89. u32 emmc_tx_data_cntl1;
  90. /*
  91. * [30:24] SDR50 mode Number of dealy elements.Each = 125pSec.
  92. * [22:16] DDR50 mode Number of dealy elements.Each = 125pSec.
  93. * [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec.
  94. * [6:0] SDR12/Compatibility mode Number of dealy elements.
  95. * Each = 125pSec.
  96. */
  97. u32 emmc_tx_data_cntl2;
  98. /*
  99. * [30:24] SDR50 mode Number of dealy elements.Each = 125pSec.
  100. * [22:16] DDR50 mode Number of dealy elements.Each = 125pSec.
  101. * [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec.
  102. * [6:0] SDR12/Compatibility mode Number of dealy elements.
  103. * Each = 125pSec.
  104. */
  105. u32 emmc_rx_cmd_data_cntl1;
  106. /*
  107. * [14:8] HS400 mode 1 Number of dealy elements.Each = 125pSec.
  108. * [6:0] HS400 mode 2 Number of dealy elements.Each = 125pSec.
  109. */
  110. u32 emmc_rx_strobe_cntl;
  111. /*
  112. * [13:8] Auto Tuning mode Number of dealy elements.Each = 125pSec.
  113. * [6:0] SDR104/HS200 Number of dealy elements.Each = 125pSec.
  114. */
  115. u32 emmc_rx_cmd_data_cntl2;
  116. /* Select the eMMC max speed allowed */
  117. u32 emmc_host_max_speed;
  118. /* Specifies on which IRQ the SCI will internally appear */
  119. u32 sci_irq;
  120. /* Configure serial IRQ (SERIRQ) line */
  121. enum serirq_mode serirq_mode;
  122. /* Configure LPSS S0ix Enable */
  123. bool lpss_s0ix_enable;
  124. /* Enable DPTF support */
  125. bool dptf_enable;
  126. /* TCC activation offset value in degrees Celsius */
  127. int tcc_offset;
  128. /*
  129. * Configure Audio clk gate and power gate
  130. * IOSF-SB port ID 92 offset 0x530 [5] and [3]
  131. */
  132. bool hdaudio_clk_gate_enable;
  133. bool hdaudio_pwr_gate_enable;
  134. bool hdaudio_bios_config_lockdown;
  135. /* SLP S3 minimum assertion width */
  136. int slp_s3_assertion_width_usecs;
  137. /* GPIO pin for PERST_0 */
  138. u32 prt0_gpio;
  139. /* USB2 eye diagram settings per port */
  140. struct usb2_eye_per_port usb2eye[MAX_USB2_PORTS];
  141. /* GPIO SD card detect pin */
  142. unsigned int sdcard_cd_gpio;
  143. /*
  144. * PRMRR size setting with three options
  145. * 0x02000000 - 32MiB
  146. * 0x04000000 - 64MiB
  147. * 0x08000000 - 128MiB
  148. */
  149. u32 PrmrrSize;
  150. /*
  151. * Enable SGX feature.
  152. * Enabling SGX feature is 2 step process,
  153. * (1) set sgx_enable = 1
  154. * (2) set PrmrrSize to supported size
  155. */
  156. bool sgx_enable;
  157. /*
  158. * Select PNP Settings.
  159. * (0) Performance,
  160. * (1) Power
  161. * (2) Power & Performance
  162. */
  163. enum pnp_settings pnp_settings;
  164. /*
  165. * PMIC PCH_PWROK delay configuration - IPC Configuration
  166. * Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address
  167. * (31:24) + Register_Offset (23:16) + OR Value (15:8) + AND Value (7:0)
  168. */
  169. u32 pmic_pmc_ipc_ctrl;
  170. /*
  171. * Options to disable XHCI Link Compliance Mode. Default is FALSE to not
  172. * disable Compliance Mode. Set TRUE to disable Compliance Mode.
  173. * 0:FALSE(Default), 1:True.
  174. */
  175. bool disable_compliance_mode;
  176. /*
  177. * Options to change USB3 ModPhy setting for the Integrated Filter (IF)
  178. * value. Default is 0 to not changing default IF value (0x12). Set
  179. * value with the range from 0x01 to 0xff to change IF value.
  180. */
  181. u32 mod_phy_if_value;
  182. /*
  183. * Options to bump USB3 LDO voltage. Default is FALSE to not increasing
  184. * LDO voltage. Set TRUE to increase LDO voltage with 40mV.
  185. * 0:FALSE (default), 1:True.
  186. */
  187. bool mod_phy_voltage_bump;
  188. /*
  189. * Options to adjust PMIC Vdd2 voltage. Default is 0 to not adjusting
  190. * the PMIC Vdd2 default voltage 1.20v. Upd for changing Vdd2 Voltage
  191. * configuration: I2C_Slave_Address (31:23) + Register_Offset (23:16)
  192. * + OR Value (15:8) + AND Value (7:0) through BUCK5_VID[3:2]:
  193. * 00=1.10v, 01=1.15v, 10=1.24v, 11=1.20v (default).
  194. */
  195. u32 pmic_vdd2_voltage;
  196. /* Option to enable VTD feature */
  197. bool enable_vtd;
  198. };
  199. static int get_config(struct udevice *dev, struct apl_config *apl)
  200. {
  201. const u8 *ptr;
  202. ofnode node;
  203. u32 emmc[4];
  204. int ret;
  205. memset(apl, '\0', sizeof(*apl));
  206. node = dev_read_subnode(dev, "fsp-s");
  207. if (!ofnode_valid(node))
  208. return log_msg_ret("fsp-s settings", -ENOENT);
  209. ptr = ofnode_read_u8_array_ptr(node, "pcie-rp-clkreq-pin",
  210. MAX_PCIE_PORTS);
  211. if (!ptr)
  212. return log_msg_ret("pcie-rp-clkreq-pin", -EINVAL);
  213. memcpy(apl->pcie_rp_clkreq_pin, ptr, MAX_PCIE_PORTS);
  214. ret = ofnode_read_u32(node, "prt0-gpio", &apl->prt0_gpio);
  215. if (ret)
  216. return log_msg_ret("prt0-gpio", ret);
  217. ret = ofnode_read_u32(node, "sdcard-cd-gpio", &apl->sdcard_cd_gpio);
  218. if (ret)
  219. return log_msg_ret("sdcard-cd-gpio", ret);
  220. ret = ofnode_read_u32_array(node, "emmc", emmc, ARRAY_SIZE(emmc));
  221. if (ret)
  222. return log_msg_ret("emmc", ret);
  223. apl->emmc_tx_data_cntl1 = emmc[0];
  224. apl->emmc_tx_data_cntl2 = emmc[1];
  225. apl->emmc_rx_cmd_data_cntl1 = emmc[2];
  226. apl->emmc_rx_cmd_data_cntl2 = emmc[3];
  227. apl->dptf_enable = ofnode_read_bool(node, "dptf-enable");
  228. apl->hdaudio_clk_gate_enable = ofnode_read_bool(node,
  229. "hdaudio-clk-gate-enable");
  230. apl->hdaudio_pwr_gate_enable = ofnode_read_bool(node,
  231. "hdaudio-pwr-gate-enable");
  232. apl->hdaudio_bios_config_lockdown = ofnode_read_bool(node,
  233. "hdaudio-bios-config-lockdown");
  234. apl->lpss_s0ix_enable = ofnode_read_bool(node, "lpss-s0ix-enable");
  235. /* Santa */
  236. apl->usb2eye[1].per_port_pe_txi_set = 7;
  237. apl->usb2eye[1].per_port_txi_set = 2;
  238. return 0;
  239. }
  240. static void apl_fsp_silicon_init_params_cb(struct apl_config *apl,
  241. struct fsp_s_config *cfg)
  242. {
  243. u8 port;
  244. for (port = 0; port < MAX_USB2_PORTS; port++) {
  245. if (apl->usb2eye[port].per_port_tx_pe_half)
  246. cfg->port_usb20_per_port_tx_pe_half[port] =
  247. apl->usb2eye[port].per_port_tx_pe_half;
  248. if (apl->usb2eye[port].per_port_pe_txi_set)
  249. cfg->port_usb20_per_port_pe_txi_set[port] =
  250. apl->usb2eye[port].per_port_pe_txi_set;
  251. if (apl->usb2eye[port].per_port_txi_set)
  252. cfg->port_usb20_per_port_txi_set[port] =
  253. apl->usb2eye[port].per_port_txi_set;
  254. if (apl->usb2eye[port].hs_skew_sel)
  255. cfg->port_usb20_hs_skew_sel[port] =
  256. apl->usb2eye[port].hs_skew_sel;
  257. if (apl->usb2eye[port].usb_tx_emphasis_en)
  258. cfg->port_usb20_i_usb_tx_emphasis_en[port] =
  259. apl->usb2eye[port].usb_tx_emphasis_en;
  260. if (apl->usb2eye[port].per_port_rxi_set)
  261. cfg->port_usb20_per_port_rxi_set[port] =
  262. apl->usb2eye[port].per_port_rxi_set;
  263. if (apl->usb2eye[port].hs_npre_drv_sel)
  264. cfg->port_usb20_hs_npre_drv_sel[port] =
  265. apl->usb2eye[port].hs_npre_drv_sel;
  266. }
  267. }
  268. int fsps_update_config(struct udevice *dev, ulong rom_offset,
  269. struct fsps_upd *upd)
  270. {
  271. struct fsp_s_config *cfg = &upd->config;
  272. struct apl_config *apl;
  273. struct binman_entry vbt;
  274. void *buf;
  275. int ret;
  276. ret = binman_entry_find("intel-vbt", &vbt);
  277. if (ret)
  278. return log_msg_ret("Cannot find VBT", ret);
  279. vbt.image_pos += rom_offset;
  280. buf = malloc(vbt.size);
  281. if (!buf)
  282. return log_msg_ret("Alloc VBT", -ENOMEM);
  283. /*
  284. * Load VBT before devicetree-specific config. This only supports
  285. * memory-mapped SPI at present.
  286. */
  287. bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
  288. memcpy(buf, (void *)vbt.image_pos, vbt.size);
  289. bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
  290. if (*(u32 *)buf != VBT_SIGNATURE)
  291. return log_msg_ret("VBT signature", -EINVAL);
  292. cfg->graphics_config_ptr = (ulong)buf;
  293. apl = malloc(sizeof(*apl));
  294. if (!apl)
  295. return log_msg_ret("config", -ENOMEM);
  296. get_config(dev, apl);
  297. cfg->ish_enable = 0;
  298. cfg->enable_sata = 0;
  299. cfg->pcie_root_port_en[2] = 0;
  300. cfg->pcie_rp_hot_plug[2] = 0;
  301. cfg->pcie_root_port_en[3] = 0;
  302. cfg->pcie_rp_hot_plug[3] = 0;
  303. cfg->pcie_root_port_en[4] = 0;
  304. cfg->pcie_rp_hot_plug[4] = 0;
  305. cfg->pcie_root_port_en[5] = 0;
  306. cfg->pcie_rp_hot_plug[5] = 0;
  307. cfg->pcie_root_port_en[1] = 0;
  308. cfg->pcie_rp_hot_plug[1] = 0;
  309. cfg->usb_otg = 0;
  310. cfg->i2c6_enable = 0;
  311. cfg->i2c7_enable = 0;
  312. cfg->hsuart3_enable = 0;
  313. cfg->spi1_enable = 0;
  314. cfg->spi2_enable = 0;
  315. cfg->sdio_enabled = 0;
  316. memcpy(cfg->pcie_rp_clk_req_number, apl->pcie_rp_clkreq_pin,
  317. sizeof(cfg->pcie_rp_clk_req_number));
  318. memcpy(cfg->pcie_rp_hot_plug, apl->pcie_rp_hotplug_enable,
  319. sizeof(cfg->pcie_rp_hot_plug));
  320. switch (apl->serirq_mode) {
  321. case SERIRQ_QUIET:
  322. cfg->sirq_enable = 1;
  323. cfg->sirq_mode = 0;
  324. break;
  325. case SERIRQ_CONTINUOUS:
  326. cfg->sirq_enable = 1;
  327. cfg->sirq_mode = 1;
  328. break;
  329. case SERIRQ_OFF:
  330. default:
  331. cfg->sirq_enable = 0;
  332. break;
  333. }
  334. if (apl->emmc_tx_cmd_cntl)
  335. cfg->emmc_tx_cmd_cntl = apl->emmc_tx_cmd_cntl;
  336. if (apl->emmc_tx_data_cntl1)
  337. cfg->emmc_tx_data_cntl1 = apl->emmc_tx_data_cntl1;
  338. if (apl->emmc_tx_data_cntl2)
  339. cfg->emmc_tx_data_cntl2 = apl->emmc_tx_data_cntl2;
  340. if (apl->emmc_rx_cmd_data_cntl1)
  341. cfg->emmc_rx_cmd_data_cntl1 = apl->emmc_rx_cmd_data_cntl1;
  342. if (apl->emmc_rx_strobe_cntl)
  343. cfg->emmc_rx_strobe_cntl = apl->emmc_rx_strobe_cntl;
  344. if (apl->emmc_rx_cmd_data_cntl2)
  345. cfg->emmc_rx_cmd_data_cntl2 = apl->emmc_rx_cmd_data_cntl2;
  346. if (apl->emmc_host_max_speed)
  347. cfg->e_mmc_host_max_speed = apl->emmc_host_max_speed;
  348. cfg->lpss_s0ix_enable = apl->lpss_s0ix_enable;
  349. cfg->skip_mp_init = true;
  350. /* Disable setting of EISS bit in FSP */
  351. cfg->spi_eiss = 0;
  352. /* Disable FSP from locking access to the RTC NVRAM */
  353. cfg->rtc_lock = 0;
  354. /* Enable Audio clk gate and power gate */
  355. cfg->hd_audio_clk_gate = apl->hdaudio_clk_gate_enable;
  356. cfg->hd_audio_pwr_gate = apl->hdaudio_pwr_gate_enable;
  357. /* Bios config lockdown Audio clk and power gate */
  358. cfg->bios_cfg_lock_down = apl->hdaudio_bios_config_lockdown;
  359. apl_fsp_silicon_init_params_cb(apl, cfg);
  360. cfg->usb_otg = true;
  361. cfg->vtd_enable = apl->enable_vtd;
  362. return 0;
  363. }
  364. static void p2sb_set_hide_bit(pci_dev_t dev, int hide)
  365. {
  366. pci_x86_clrset_config(dev, PCH_P2SB_E0 + 1, HIDE_BIT,
  367. hide ? HIDE_BIT : 0, PCI_SIZE_8);
  368. }
  369. /* Configure package power limits */
  370. static int set_power_limits(struct udevice *dev)
  371. {
  372. msr_t rapl_msr_reg, limit;
  373. u32 power_unit;
  374. u32 tdp, min_power, max_power;
  375. u32 pl2_val;
  376. u32 override_tdp[2];
  377. int ret;
  378. /* Get units */
  379. rapl_msr_reg = msr_read(MSR_PKG_POWER_SKU_UNIT);
  380. power_unit = 1 << (rapl_msr_reg.lo & 0xf);
  381. /* Get power defaults for this SKU */
  382. rapl_msr_reg = msr_read(MSR_PKG_POWER_SKU);
  383. tdp = rapl_msr_reg.lo & PKG_POWER_LIMIT_MASK;
  384. pl2_val = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK;
  385. min_power = (rapl_msr_reg.lo >> 16) & PKG_POWER_LIMIT_MASK;
  386. max_power = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK;
  387. if (min_power > 0 && tdp < min_power)
  388. tdp = min_power;
  389. if (max_power > 0 && tdp > max_power)
  390. tdp = max_power;
  391. ret = dev_read_u32_array(dev, "tdp-pl-override-mw", override_tdp,
  392. ARRAY_SIZE(override_tdp));
  393. if (ret)
  394. return log_msg_ret("tdp-pl-override-mw", ret);
  395. /* Set PL1 override value */
  396. if (override_tdp[0])
  397. tdp = override_tdp[0] * power_unit / 1000;
  398. /* Set PL2 override value */
  399. if (override_tdp[1])
  400. pl2_val = override_tdp[1] * power_unit / 1000;
  401. /* Set long term power limit to TDP */
  402. limit.lo = tdp & PKG_POWER_LIMIT_MASK;
  403. /* Set PL1 Pkg Power clamp bit */
  404. limit.lo |= PKG_POWER_LIMIT_CLAMP;
  405. limit.lo |= PKG_POWER_LIMIT_EN;
  406. limit.lo |= (MB_POWER_LIMIT1_TIME_DEFAULT &
  407. PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT;
  408. /* Set short term power limit PL2 */
  409. limit.hi = pl2_val & PKG_POWER_LIMIT_MASK;
  410. limit.hi |= PKG_POWER_LIMIT_EN;
  411. /* Program package power limits in RAPL MSR */
  412. msr_write(MSR_PKG_POWER_LIMIT, limit);
  413. log_info("RAPL PL1 %d.%dW\n", tdp / power_unit,
  414. 100 * (tdp % power_unit) / power_unit);
  415. log_info("RAPL PL2 %d.%dW\n", pl2_val / power_unit,
  416. 100 * (pl2_val % power_unit) / power_unit);
  417. /*
  418. * Sett RAPL MMIO register for Power limits. RAPL driver is using MSR
  419. * instead of MMIO, so disable LIMIT_EN bit for MMIO
  420. */
  421. writel(limit.lo & ~PKG_POWER_LIMIT_EN, MCHBAR_REG(MCHBAR_RAPL_PPL));
  422. writel(limit.hi & ~PKG_POWER_LIMIT_EN, MCHBAR_REG(MCHBAR_RAPL_PPL + 4));
  423. return 0;
  424. }
  425. int p2sb_unhide(void)
  426. {
  427. pci_dev_t dev = PCI_BDF(0, 0xd, 0);
  428. ulong val;
  429. p2sb_set_hide_bit(dev, 0);
  430. pci_x86_read_config(dev, PCI_VENDOR_ID, &val, PCI_SIZE_16);
  431. if (val != PCI_VENDOR_ID_INTEL)
  432. return log_msg_ret("p2sb unhide", -EIO);
  433. return 0;
  434. }
  435. /* Overwrites the SCI IRQ if another IRQ number is given by device tree */
  436. static void set_sci_irq(void)
  437. {
  438. /* Skip this for now */
  439. }
  440. int arch_fsps_preinit(void)
  441. {
  442. struct udevice *itss;
  443. int ret;
  444. ret = irq_first_device_type(X86_IRQT_ITSS, &itss);
  445. if (ret)
  446. return log_msg_ret("no itss", ret);
  447. /*
  448. * Snapshot the current GPIO IRQ polarities. FSP is setting a default
  449. * policy that doesn't honour boards' requirements
  450. */
  451. irq_snapshot_polarities(itss);
  452. /*
  453. * Clear the GPI interrupt status and enable registers. These
  454. * registers do not get reset to default state when booting from S5.
  455. */
  456. ret = pinctrl_gpi_clear_int_cfg();
  457. if (ret)
  458. return log_msg_ret("gpi_clear", ret);
  459. return 0;
  460. }
  461. int arch_fsp_init_r(void)
  462. {
  463. #ifdef CONFIG_HAVE_ACPI_RESUME
  464. bool s3wake = gd->arch.prev_sleep_state == ACPI_S3;
  465. #else
  466. bool s3wake = false;
  467. #endif
  468. struct udevice *dev, *itss;
  469. int ret;
  470. if (!ll_boot_init())
  471. return 0;
  472. /*
  473. * This must be called before any devices are probed. Put any probing
  474. * into arch_fsps_preinit() above.
  475. *
  476. * We don't use CONFIG_APL_BOOT_FROM_FAST_SPI_FLASH here since it will
  477. * force PCI to be probed.
  478. */
  479. ret = fsp_silicon_init(s3wake, false);
  480. if (ret)
  481. return ret;
  482. ret = irq_first_device_type(X86_IRQT_ITSS, &itss);
  483. if (ret)
  484. return log_msg_ret("no itss", ret);
  485. /* Restore GPIO IRQ polarities back to previous settings */
  486. irq_restore_polarities(itss);
  487. /* soc_init() */
  488. ret = p2sb_unhide();
  489. if (ret)
  490. return log_msg_ret("unhide p2sb", ret);
  491. /* Set RAPL MSR for Package power limits*/
  492. ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev);
  493. if (ret)
  494. return log_msg_ret("Cannot get northbridge", ret);
  495. set_power_limits(dev);
  496. /*
  497. * FSP-S routes SCI to IRQ 9. With the help of this function you can
  498. * select another IRQ for SCI.
  499. */
  500. set_sci_irq();
  501. return 0;
  502. }