ddr3_training_ip_def.h 3.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) Marvell International Ltd. and its affiliates
  4. */
  5. #ifndef _DDR3_TRAINING_IP_DEF_H
  6. #define _DDR3_TRAINING_IP_DEF_H
  7. #define PATTERN_55 0x55555555
  8. #define PATTERN_AA 0xaaaaaaaa
  9. #define PATTERN_80 0x80808080
  10. #define PATTERN_20 0x20202020
  11. #define PATTERN_01 0x01010101
  12. #define PATTERN_FF 0xffffffff
  13. #define PATTERN_00 0x00000000
  14. /* 16bit bus width patterns */
  15. #define PATTERN_55AA 0x5555aaaa
  16. #define PATTERN_00FF 0x0000ffff
  17. #define PATTERN_0080 0x00008080
  18. #define INVALID_VALUE 0xffffffff
  19. #define MAX_NUM_OF_DUNITS 32
  20. /*
  21. * length *2 = length in words of pattern, first low address,
  22. * second high address
  23. */
  24. #define TEST_PATTERN_LENGTH 4
  25. #define KILLER_PATTERN_DQ_NUMBER 8
  26. #define SSO_DQ_NUMBER 4
  27. #define PATTERN_MAXIMUM_LENGTH 64
  28. #define ADLL_TX_LENGTH 64
  29. #define ADLL_RX_LENGTH 32
  30. #define PARAM_NOT_CARE 0
  31. #define PARAM_UNDEFINED 0xffffffff
  32. #define READ_LEVELING_PHY_OFFSET 2
  33. #define WRITE_LEVELING_PHY_OFFSET 0
  34. #define MASK_ALL_BITS 0xffffffff
  35. #define CS_BIT_MASK 0xf
  36. /* DFX access */
  37. #define BROADCAST_ID 28
  38. #define MULTICAST_ID 29
  39. #define XSB_BASE_ADDR 0x00004000
  40. #define XSB_CTRL_0_REG 0x00000000
  41. #define XSB_CTRL_1_REG 0x00000004
  42. #define XSB_CMD_REG 0x00000008
  43. #define XSB_ADDRESS_REG 0x0000000c
  44. #define XSB_DATA_REG 0x00000010
  45. #define PIPE_ENABLE_ADDR 0x000f8000
  46. #define ENABLE_DDR_TUNING_ADDR 0x000f829c
  47. #define CLIENT_BASE_ADDR 0x00002000
  48. #define CLIENT_CTRL_REG 0x00000000
  49. #define TARGET_INT 0x1801
  50. #define TARGET_EXT 0x180e
  51. #define BYTE_EN 0
  52. #define CMD_READ 0
  53. #define CMD_WRITE 1
  54. #define INTERNAL_ACCESS_PORT 1
  55. #define EXECUTING 1
  56. #define ACCESS_EXT 1
  57. #define CS2_EXIST_BIT 2
  58. #define TRAINING_ID 0xf
  59. #define EXT_TRAINING_ID 1
  60. #define EXT_MODE 0x4
  61. #define GET_RESULT_STATE(res) (res)
  62. #define SET_RESULT_STATE(res, state) (res = state)
  63. #define ADDR_SIZE_512MB 0x04000000
  64. #define ADDR_SIZE_1GB 0x08000000
  65. #define ADDR_SIZE_2GB 0x10000000
  66. #define ADDR_SIZE_4GB 0x20000000
  67. #define ADDR_SIZE_8GB 0x40000000
  68. #define ADDR_SIZE_16GB 0x80000000
  69. enum hws_edge_compare {
  70. EDGE_PF,
  71. EDGE_FP,
  72. EDGE_FPF,
  73. EDGE_PFP
  74. };
  75. enum hws_control_element {
  76. HWS_CONTROL_ELEMENT_ADLL, /* per bit 1 edge */
  77. HWS_CONTROL_ELEMENT_DQ_SKEW,
  78. HWS_CONTROL_ELEMENT_DQS_SKEW
  79. };
  80. enum hws_search_dir {
  81. HWS_LOW2HIGH,
  82. HWS_HIGH2LOW,
  83. HWS_SEARCH_DIR_LIMIT
  84. };
  85. enum hws_operation {
  86. OPERATION_READ = 0,
  87. OPERATION_WRITE = 1
  88. };
  89. enum hws_training_ip_stat {
  90. HWS_TRAINING_IP_STATUS_FAIL,
  91. HWS_TRAINING_IP_STATUS_SUCCESS,
  92. HWS_TRAINING_IP_STATUS_TIMEOUT
  93. };
  94. enum hws_ddr_cs {
  95. CS_SINGLE,
  96. CS_NON_SINGLE
  97. };
  98. enum hws_ddr_phy {
  99. DDR_PHY_DATA = 0,
  100. DDR_PHY_CONTROL = 1
  101. };
  102. enum hws_dir {
  103. OPER_WRITE,
  104. OPER_READ,
  105. OPER_WRITE_AND_READ
  106. };
  107. enum hws_wl_supp {
  108. PHASE_SHIFT,
  109. CLOCK_SHIFT,
  110. ALIGN_SHIFT
  111. };
  112. enum mv_ddr_tip_bit_state {
  113. BIT_LOW_UI,
  114. BIT_HIGH_UI,
  115. BIT_SPLIT_IN,
  116. BIT_SPLIT_OUT,
  117. BIT_STATE_LAST
  118. };
  119. enum mv_ddr_tip_byte_state{
  120. BYTE_NOT_DEFINED,
  121. BYTE_HOMOGENEOUS_LOW = 0x1,
  122. BYTE_HOMOGENEOUS_HIGH = 0x2,
  123. BYTE_HOMOGENEOUS_SPLIT_IN = 0x4,
  124. BYTE_HOMOGENEOUS_SPLIT_OUT = 0x8,
  125. BYTE_SPLIT_OUT_MIX = 0x10,
  126. BYTE_STATE_LAST
  127. };
  128. struct reg_data {
  129. unsigned int reg_addr;
  130. unsigned int reg_data;
  131. unsigned int reg_mask;
  132. };
  133. enum dm_direction {
  134. DM_DIR_INVERSE,
  135. DM_DIR_DIRECT
  136. };
  137. #endif /* _DDR3_TRAINING_IP_DEF_H */