t4240qds.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2009-2012 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <env.h>
  8. #include <i2c.h>
  9. #include <init.h>
  10. #include <irq_func.h>
  11. #include <netdev.h>
  12. #include <linux/compiler.h>
  13. #include <asm/mmu.h>
  14. #include <asm/processor.h>
  15. #include <asm/cache.h>
  16. #include <asm/immap_85xx.h>
  17. #include <asm/fsl_law.h>
  18. #include <asm/fsl_serdes.h>
  19. #include <asm/fsl_liodn.h>
  20. #include <fm_eth.h>
  21. #include "../common/qixis.h"
  22. #include "../common/vsc3316_3308.h"
  23. #include "t4qds.h"
  24. #include "t4240qds_qixis.h"
  25. DECLARE_GLOBAL_DATA_PTR;
  26. static int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
  27. {8, 8}, {9, 9}, {14, 14}, {15, 15} };
  28. static int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
  29. {10, 10}, {11, 11}, {12, 12}, {13, 13} };
  30. static int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
  31. {10, 11}, {11, 10}, {12, 2}, {13, 3} };
  32. static int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
  33. {8, 9}, {9, 8}, {14, 1}, {15, 0} };
  34. int checkboard(void)
  35. {
  36. char buf[64];
  37. u8 sw;
  38. struct cpu_type *cpu = gd->arch.cpu;
  39. unsigned int i;
  40. printf("Board: %sQDS, ", cpu->name);
  41. printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
  42. QIXIS_READ(id), QIXIS_READ(arch));
  43. sw = QIXIS_READ(brdcfg[0]);
  44. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  45. if (sw < 0x8)
  46. printf("vBank: %d\n", sw);
  47. else if (sw == 0x8)
  48. puts("Promjet\n");
  49. else if (sw == 0x9)
  50. puts("NAND\n");
  51. else
  52. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  53. printf("FPGA: v%d (%s), build %d",
  54. (int)QIXIS_READ(scver), qixis_read_tag(buf),
  55. (int)qixis_read_minor());
  56. /* the timestamp string contains "\n" at the end */
  57. printf(" on %s", qixis_read_time(buf));
  58. /*
  59. * Display the actual SERDES reference clocks as configured by the
  60. * dip switches on the board. Note that the SWx registers could
  61. * technically be set to force the reference clocks to match the
  62. * values that the SERDES expects (or vice versa). For now, however,
  63. * we just display both values and hope the user notices when they
  64. * don't match.
  65. */
  66. puts("SERDES Reference Clocks: ");
  67. sw = QIXIS_READ(brdcfg[2]);
  68. for (i = 0; i < MAX_SERDES; i++) {
  69. static const char * const freq[] = {
  70. "100", "125", "156.25", "161.1328125"};
  71. unsigned int clock = (sw >> (6 - 2 * i)) & 3;
  72. printf("SERDES%u=%sMHz ", i+1, freq[clock]);
  73. }
  74. puts("\n");
  75. return 0;
  76. }
  77. int select_i2c_ch_pca9547(u8 ch)
  78. {
  79. int ret;
  80. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  81. if (ret) {
  82. puts("PCA: failed to select proper channel\n");
  83. return ret;
  84. }
  85. return 0;
  86. }
  87. /*
  88. * read_voltage from sensor on I2C bus
  89. * We use average of 4 readings, waiting for 532us befor another reading
  90. */
  91. #define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */
  92. #define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */
  93. static inline int read_voltage(void)
  94. {
  95. int i, ret, voltage_read = 0;
  96. u16 vol_mon;
  97. for (i = 0; i < NUM_READINGS; i++) {
  98. ret = i2c_read(I2C_VOL_MONITOR_ADDR,
  99. I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
  100. if (ret) {
  101. printf("VID: failed to read core voltage\n");
  102. return ret;
  103. }
  104. if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
  105. printf("VID: Core voltage sensor error\n");
  106. return -1;
  107. }
  108. debug("VID: bus voltage reads 0x%04x\n", vol_mon);
  109. /* LSB = 4mv */
  110. voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
  111. udelay(WAIT_FOR_ADC);
  112. }
  113. /* calculate the average */
  114. voltage_read /= NUM_READINGS;
  115. return voltage_read;
  116. }
  117. /*
  118. * We need to calculate how long before the voltage starts to drop or increase
  119. * It returns with the loop count. Each loop takes several readings (532us)
  120. */
  121. static inline int wait_for_voltage_change(int vdd_last)
  122. {
  123. int timeout, vdd_current;
  124. vdd_current = read_voltage();
  125. /* wait until voltage starts to drop */
  126. for (timeout = 0; abs(vdd_last - vdd_current) <= 4 &&
  127. timeout < 100; timeout++) {
  128. vdd_current = read_voltage();
  129. }
  130. if (timeout >= 100) {
  131. printf("VID: Voltage adjustment timeout\n");
  132. return -1;
  133. }
  134. return timeout;
  135. }
  136. /*
  137. * argument 'wait' is the time we know the voltage difference can be measured
  138. * this function keeps reading the voltage until it is stable
  139. */
  140. static inline int wait_for_voltage_stable(int wait)
  141. {
  142. int timeout, vdd_current, vdd_last;
  143. vdd_last = read_voltage();
  144. udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
  145. /* wait until voltage is stable */
  146. vdd_current = read_voltage();
  147. for (timeout = 0; abs(vdd_last - vdd_current) >= 4 &&
  148. timeout < 100; timeout++) {
  149. vdd_last = vdd_current;
  150. udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
  151. vdd_current = read_voltage();
  152. }
  153. if (timeout >= 100) {
  154. printf("VID: Voltage adjustment timeout\n");
  155. return -1;
  156. }
  157. return vdd_current;
  158. }
  159. static inline int set_voltage(u8 vid)
  160. {
  161. int wait, vdd_last;
  162. vdd_last = read_voltage();
  163. QIXIS_WRITE(brdcfg[6], vid);
  164. wait = wait_for_voltage_change(vdd_last);
  165. if (wait < 0)
  166. return -1;
  167. debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC);
  168. wait = wait ? wait : 1;
  169. vdd_last = wait_for_voltage_stable(wait);
  170. if (vdd_last < 0)
  171. return -1;
  172. debug("VID: Current voltage is %d mV\n", vdd_last);
  173. return vdd_last;
  174. }
  175. static int adjust_vdd(ulong vdd_override)
  176. {
  177. int re_enable = disable_interrupts();
  178. ccsr_gur_t __iomem *gur =
  179. (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  180. u32 fusesr;
  181. u8 vid, vid_current;
  182. int vdd_target, vdd_current, vdd_last;
  183. int ret;
  184. unsigned long vdd_string_override;
  185. char *vdd_string;
  186. static const uint16_t vdd[32] = {
  187. 0, /* unused */
  188. 9875, /* 0.9875V */
  189. 9750,
  190. 9625,
  191. 9500,
  192. 9375,
  193. 9250,
  194. 9125,
  195. 9000,
  196. 8875,
  197. 8750,
  198. 8625,
  199. 8500,
  200. 8375,
  201. 8250,
  202. 8125,
  203. 10000, /* 1.0000V */
  204. 10125,
  205. 10250,
  206. 10375,
  207. 10500,
  208. 10625,
  209. 10750,
  210. 10875,
  211. 11000,
  212. 0, /* reserved */
  213. };
  214. struct vdd_drive {
  215. u8 vid;
  216. unsigned voltage;
  217. };
  218. ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR);
  219. if (ret) {
  220. debug("VID: I2c failed to switch channel\n");
  221. ret = -1;
  222. goto exit;
  223. }
  224. /* get the voltage ID from fuse status register */
  225. fusesr = in_be32(&gur->dcfg_fusesr);
  226. vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
  227. FSL_CORENET_DCFG_FUSESR_VID_MASK;
  228. if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
  229. vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
  230. FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
  231. }
  232. vdd_target = vdd[vid];
  233. /* check override variable for overriding VDD */
  234. vdd_string = env_get("t4240qds_vdd_mv");
  235. if (vdd_override == 0 && vdd_string &&
  236. !strict_strtoul(vdd_string, 10, &vdd_string_override))
  237. vdd_override = vdd_string_override;
  238. if (vdd_override >= 819 && vdd_override <= 1212) {
  239. vdd_target = vdd_override * 10; /* convert to 1/10 mV */
  240. debug("VDD override is %lu\n", vdd_override);
  241. } else if (vdd_override != 0) {
  242. printf("Invalid value.\n");
  243. }
  244. if (vdd_target == 0) {
  245. debug("VID: VID not used\n");
  246. ret = 0;
  247. goto exit;
  248. } else {
  249. /* round up and divice by 10 to get a value in mV */
  250. vdd_target = DIV_ROUND_UP(vdd_target, 10);
  251. debug("VID: vid = %d mV\n", vdd_target);
  252. }
  253. /*
  254. * Check current board VID setting
  255. * Voltage regulator support output to 6.250mv step
  256. * The highes voltage allowed for this board is (vid=0x40) 1.21250V
  257. * the lowest is (vid=0x7f) 0.81875V
  258. */
  259. vid_current = QIXIS_READ(brdcfg[6]);
  260. vdd_current = 121250 - (vid_current - 0x40) * 625;
  261. debug("VID: Current vid setting is (0x%x) %d mV\n",
  262. vid_current, vdd_current/100);
  263. /*
  264. * Read voltage monitor to check real voltage.
  265. * Voltage monitor LSB is 4mv.
  266. */
  267. vdd_last = read_voltage();
  268. if (vdd_last < 0) {
  269. printf("VID: Could not read voltage sensor abort VID adjustment\n");
  270. ret = -1;
  271. goto exit;
  272. }
  273. debug("VID: Core voltage is at %d mV\n", vdd_last);
  274. /*
  275. * Adjust voltage to at or 8mV above target.
  276. * Each step of adjustment is 6.25mV.
  277. * Stepping down too fast may cause over current.
  278. */
  279. while (vdd_last > 0 && vid_current < 0x80 &&
  280. vdd_last > (vdd_target + 8)) {
  281. vid_current++;
  282. vdd_last = set_voltage(vid_current);
  283. }
  284. /*
  285. * Check if we need to step up
  286. * This happens when board voltage switch was set too low
  287. */
  288. while (vdd_last > 0 && vid_current >= 0x40 &&
  289. vdd_last < vdd_target + 2) {
  290. vid_current--;
  291. vdd_last = set_voltage(vid_current);
  292. }
  293. if (vdd_last > 0)
  294. printf("VID: Core voltage %d mV\n", vdd_last);
  295. else
  296. ret = -1;
  297. exit:
  298. if (re_enable)
  299. enable_interrupts();
  300. return ret;
  301. }
  302. /* Configure Crossbar switches for Front-Side SerDes Ports */
  303. int config_frontside_crossbar_vsc3316(void)
  304. {
  305. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  306. u32 srds_prtcl_s1, srds_prtcl_s2;
  307. int ret;
  308. ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS);
  309. if (ret)
  310. return ret;
  311. srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
  312. FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  313. srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  314. switch (srds_prtcl_s1) {
  315. case 37:
  316. case 38:
  317. /* swap first lane and third lane on slot1 */
  318. vsc3316_fsm1_tx[0][1] = 14;
  319. vsc3316_fsm1_tx[6][1] = 0;
  320. vsc3316_fsm1_rx[1][1] = 2;
  321. vsc3316_fsm1_rx[6][1] = 13;
  322. case 39:
  323. case 40:
  324. case 45:
  325. case 46:
  326. case 47:
  327. case 48:
  328. /* swap first lane and third lane on slot2 */
  329. vsc3316_fsm1_tx[2][1] = 8;
  330. vsc3316_fsm1_tx[4][1] = 6;
  331. vsc3316_fsm1_rx[2][1] = 10;
  332. vsc3316_fsm1_rx[5][1] = 5;
  333. default:
  334. ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8);
  335. if (ret)
  336. return ret;
  337. ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8);
  338. if (ret)
  339. return ret;
  340. break;
  341. }
  342. srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
  343. FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
  344. srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
  345. switch (srds_prtcl_s2) {
  346. case 37:
  347. case 38:
  348. /* swap first lane and third lane on slot3 */
  349. vsc3316_fsm2_tx[2][1] = 11;
  350. vsc3316_fsm2_tx[5][1] = 4;
  351. vsc3316_fsm2_rx[2][1] = 9;
  352. vsc3316_fsm2_rx[4][1] = 7;
  353. case 39:
  354. case 40:
  355. case 45:
  356. case 46:
  357. case 47:
  358. case 48:
  359. case 49:
  360. case 50:
  361. case 51:
  362. case 52:
  363. case 53:
  364. case 54:
  365. /* swap first lane and third lane on slot4 */
  366. vsc3316_fsm2_tx[6][1] = 3;
  367. vsc3316_fsm2_tx[1][1] = 12;
  368. vsc3316_fsm2_rx[0][1] = 1;
  369. vsc3316_fsm2_rx[6][1] = 15;
  370. default:
  371. ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8);
  372. if (ret)
  373. return ret;
  374. ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8);
  375. if (ret)
  376. return ret;
  377. break;
  378. }
  379. return 0;
  380. }
  381. int config_backside_crossbar_mux(void)
  382. {
  383. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  384. u32 srds_prtcl_s3, srds_prtcl_s4;
  385. u8 brdcfg;
  386. srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) &
  387. FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
  388. srds_prtcl_s3 >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
  389. switch (srds_prtcl_s3) {
  390. case 0:
  391. /* SerDes3 is not enabled */
  392. break;
  393. case 1:
  394. case 2:
  395. case 9:
  396. case 10:
  397. /* SD3(0:7) => SLOT5(0:7) */
  398. brdcfg = QIXIS_READ(brdcfg[12]);
  399. brdcfg &= ~BRDCFG12_SD3MX_MASK;
  400. brdcfg |= BRDCFG12_SD3MX_SLOT5;
  401. QIXIS_WRITE(brdcfg[12], brdcfg);
  402. break;
  403. case 3:
  404. case 4:
  405. case 5:
  406. case 6:
  407. case 7:
  408. case 8:
  409. case 11:
  410. case 12:
  411. case 13:
  412. case 14:
  413. case 15:
  414. case 16:
  415. case 17:
  416. case 18:
  417. case 19:
  418. case 20:
  419. /* SD3(4:7) => SLOT6(0:3) */
  420. brdcfg = QIXIS_READ(brdcfg[12]);
  421. brdcfg &= ~BRDCFG12_SD3MX_MASK;
  422. brdcfg |= BRDCFG12_SD3MX_SLOT6;
  423. QIXIS_WRITE(brdcfg[12], brdcfg);
  424. break;
  425. default:
  426. printf("WARNING: unsupported for SerDes3 Protocol %d\n",
  427. srds_prtcl_s3);
  428. return -1;
  429. }
  430. srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
  431. FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
  432. srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
  433. switch (srds_prtcl_s4) {
  434. case 0:
  435. /* SerDes4 is not enabled */
  436. break;
  437. case 1:
  438. case 2:
  439. /* 10b, SD4(0:7) => SLOT7(0:7) */
  440. brdcfg = QIXIS_READ(brdcfg[12]);
  441. brdcfg &= ~BRDCFG12_SD4MX_MASK;
  442. brdcfg |= BRDCFG12_SD4MX_SLOT7;
  443. QIXIS_WRITE(brdcfg[12], brdcfg);
  444. break;
  445. case 3:
  446. case 4:
  447. case 5:
  448. case 6:
  449. case 7:
  450. case 8:
  451. /* x1b, SD4(4:7) => SLOT8(0:3) */
  452. brdcfg = QIXIS_READ(brdcfg[12]);
  453. brdcfg &= ~BRDCFG12_SD4MX_MASK;
  454. brdcfg |= BRDCFG12_SD4MX_SLOT8;
  455. QIXIS_WRITE(brdcfg[12], brdcfg);
  456. break;
  457. case 9:
  458. case 10:
  459. case 11:
  460. case 12:
  461. case 13:
  462. case 14:
  463. case 15:
  464. case 16:
  465. case 18:
  466. /* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */
  467. brdcfg = QIXIS_READ(brdcfg[12]);
  468. brdcfg &= ~BRDCFG12_SD4MX_MASK;
  469. brdcfg |= BRDCFG12_SD4MX_AURO_SATA;
  470. QIXIS_WRITE(brdcfg[12], brdcfg);
  471. break;
  472. default:
  473. printf("WARNING: unsupported for SerDes4 Protocol %d\n",
  474. srds_prtcl_s4);
  475. return -1;
  476. }
  477. return 0;
  478. }
  479. int board_early_init_r(void)
  480. {
  481. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  482. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  483. /*
  484. * Remap Boot flash + PROMJET region to caching-inhibited
  485. * so that flash can be erased properly.
  486. */
  487. /* Flush d-cache and invalidate i-cache of any FLASH data */
  488. flush_dcache();
  489. invalidate_icache();
  490. if (flash_esel == -1) {
  491. /* very unlikely unless something is messed up */
  492. puts("Error: Could not find TLB for FLASH BASE\n");
  493. flash_esel = 2; /* give our best effort to continue */
  494. } else {
  495. /* invalidate existing TLB entry for flash + promjet */
  496. disable_tlb(flash_esel);
  497. }
  498. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  499. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  500. 0, flash_esel, BOOKE_PAGESZ_256M, 1);
  501. /* Disable remote I2C connection to qixis fpga */
  502. QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
  503. /*
  504. * Adjust core voltage according to voltage ID
  505. * This function changes I2C mux to channel 2.
  506. */
  507. if (adjust_vdd(0))
  508. printf("Warning: Adjusting core voltage failed.\n");
  509. /* Configure board SERDES ports crossbar */
  510. config_frontside_crossbar_vsc3316();
  511. config_backside_crossbar_mux();
  512. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  513. return 0;
  514. }
  515. unsigned long get_board_sys_clk(void)
  516. {
  517. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  518. #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
  519. /* use accurate clock measurement */
  520. int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
  521. int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
  522. u32 val;
  523. val = freq * base;
  524. if (val) {
  525. debug("SYS Clock measurement is: %d\n", val);
  526. return val;
  527. } else {
  528. printf("Warning: SYS clock measurement is invalid, using value from brdcfg1.\n");
  529. }
  530. #endif
  531. switch (sysclk_conf & 0x0F) {
  532. case QIXIS_SYSCLK_83:
  533. return 83333333;
  534. case QIXIS_SYSCLK_100:
  535. return 100000000;
  536. case QIXIS_SYSCLK_125:
  537. return 125000000;
  538. case QIXIS_SYSCLK_133:
  539. return 133333333;
  540. case QIXIS_SYSCLK_150:
  541. return 150000000;
  542. case QIXIS_SYSCLK_160:
  543. return 160000000;
  544. case QIXIS_SYSCLK_166:
  545. return 166666666;
  546. }
  547. return 66666666;
  548. }
  549. unsigned long get_board_ddr_clk(void)
  550. {
  551. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  552. #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
  553. /* use accurate clock measurement */
  554. int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
  555. int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
  556. u32 val;
  557. val = freq * base;
  558. if (val) {
  559. debug("DDR Clock measurement is: %d\n", val);
  560. return val;
  561. } else {
  562. printf("Warning: DDR clock measurement is invalid, using value from brdcfg1.\n");
  563. }
  564. #endif
  565. switch ((ddrclk_conf & 0x30) >> 4) {
  566. case QIXIS_DDRCLK_100:
  567. return 100000000;
  568. case QIXIS_DDRCLK_125:
  569. return 125000000;
  570. case QIXIS_DDRCLK_133:
  571. return 133333333;
  572. }
  573. return 66666666;
  574. }
  575. int misc_init_r(void)
  576. {
  577. u8 sw;
  578. void *srds_base = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  579. serdes_corenet_t *srds_regs;
  580. u32 actual[MAX_SERDES];
  581. u32 pllcr0, expected;
  582. unsigned int i;
  583. sw = QIXIS_READ(brdcfg[2]);
  584. for (i = 0; i < MAX_SERDES; i++) {
  585. unsigned int clock = (sw >> (6 - 2 * i)) & 3;
  586. switch (clock) {
  587. case 0:
  588. actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
  589. break;
  590. case 1:
  591. actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
  592. break;
  593. case 2:
  594. actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
  595. break;
  596. case 3:
  597. actual[i] = SRDS_PLLCR0_RFCK_SEL_161_13;
  598. break;
  599. }
  600. }
  601. for (i = 0; i < MAX_SERDES; i++) {
  602. srds_regs = srds_base + i * 0x1000;
  603. pllcr0 = srds_regs->bank[0].pllcr0;
  604. expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
  605. if (expected != actual[i]) {
  606. printf("Warning: SERDES%u expects reference clock %sMHz, but actual is %sMHz\n",
  607. i + 1, serdes_clock_to_string(expected),
  608. serdes_clock_to_string(actual[i]));
  609. }
  610. }
  611. return 0;
  612. }
  613. int ft_board_setup(void *blob, bd_t *bd)
  614. {
  615. phys_addr_t base;
  616. phys_size_t size;
  617. ft_cpu_setup(blob, bd);
  618. base = env_get_bootm_low();
  619. size = env_get_bootm_size();
  620. fdt_fixup_memory(blob, (u64)base, (u64)size);
  621. #ifdef CONFIG_PCI
  622. pci_of_setup(blob, bd);
  623. #endif
  624. fdt_fixup_liodn(blob);
  625. fsl_fdt_fixup_dr_usb(blob, bd);
  626. #ifdef CONFIG_SYS_DPAA_FMAN
  627. fdt_fixup_fman_ethernet(blob);
  628. fdt_fixup_board_enet(blob);
  629. #endif
  630. return 0;
  631. }
  632. /*
  633. * This function is called by bdinfo to print detail board information.
  634. * As an exmaple for future board, we organize the messages into
  635. * several sections. If applicable, the message is in the format of
  636. * <name> = <value>
  637. * It should aligned with normal output of bdinfo command.
  638. *
  639. * Voltage: Core, DDR and another configurable voltages
  640. * Clock : Critical clocks which are not printed already
  641. * RCW : RCW source if not printed already
  642. * Misc : Other important information not in above catagories
  643. */
  644. void board_detail(void)
  645. {
  646. int i;
  647. u8 brdcfg[16], dutcfg[16], rst_ctl;
  648. int vdd, rcwsrc;
  649. static const char * const clk[] = {"66.67", "100", "125", "133.33"};
  650. for (i = 0; i < 16; i++) {
  651. brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
  652. dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
  653. }
  654. /* Voltage secion */
  655. if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR)) {
  656. vdd = read_voltage();
  657. if (vdd > 0)
  658. printf("Core voltage= %d mV\n", vdd);
  659. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  660. }
  661. printf("XVDD = 1.%d V\n", ((brdcfg[8] & 0xf) - 4) * 5 + 25);
  662. /* clock section */
  663. printf("SYSCLK = %s MHz\nDDRCLK = %s MHz\n",
  664. clk[(brdcfg[11] >> 2) & 0x3], clk[brdcfg[11] & 3]);
  665. /* RCW section */
  666. rcwsrc = (dutcfg[0] << 1) + (dutcfg[1] & 1);
  667. puts("RCW source = ");
  668. switch (rcwsrc) {
  669. case 0x017:
  670. case 0x01f:
  671. puts("8-bit NOR\n");
  672. break;
  673. case 0x027:
  674. case 0x02F:
  675. puts("16-bit NOR\n");
  676. break;
  677. case 0x040:
  678. puts("SDHC/eMMC\n");
  679. break;
  680. case 0x044:
  681. puts("SPI 16-bit addressing\n");
  682. break;
  683. case 0x045:
  684. puts("SPI 24-bit addressing\n");
  685. break;
  686. case 0x048:
  687. puts("I2C normal addressing\n");
  688. break;
  689. case 0x049:
  690. puts("I2C extended addressing\n");
  691. break;
  692. case 0x108:
  693. case 0x109:
  694. case 0x10a:
  695. case 0x10b:
  696. puts("8-bit NAND, 2KB\n");
  697. break;
  698. default:
  699. if ((rcwsrc >= 0x080) && (rcwsrc <= 0x09f))
  700. puts("Hard-coded RCW\n");
  701. else if ((rcwsrc >= 0x110) && (rcwsrc <= 0x11f))
  702. puts("8-bit NAND, 4KB\n");
  703. else
  704. puts("unknown\n");
  705. break;
  706. }
  707. /* Misc section */
  708. rst_ctl = QIXIS_READ(rst_ctl);
  709. puts("HRESET_REQ = ");
  710. switch (rst_ctl & 0x30) {
  711. case 0x00:
  712. puts("Ignored\n");
  713. break;
  714. case 0x10:
  715. puts("Assert HRESET\n");
  716. break;
  717. case 0x30:
  718. puts("Reset system\n");
  719. break;
  720. default:
  721. puts("N/A\n");
  722. break;
  723. }
  724. }
  725. /*
  726. * Reverse engineering switch settings.
  727. * Some bits cannot be figured out. They will be displayed as
  728. * underscore in binary format. mask[] has those bits.
  729. * Some bits are calculated differently than the actual switches
  730. * if booting with overriding by FPGA.
  731. */
  732. void qixis_dump_switch(void)
  733. {
  734. int i;
  735. u8 sw[9];
  736. /*
  737. * Any bit with 1 means that bit cannot be reverse engineered.
  738. * It will be displayed as _ in binary format.
  739. */
  740. static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xcf, 0x3f, 0x1f};
  741. char buf[10];
  742. u8 brdcfg[16], dutcfg[16];
  743. for (i = 0; i < 16; i++) {
  744. brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
  745. dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
  746. }
  747. sw[0] = dutcfg[0];
  748. sw[1] = (dutcfg[1] << 0x07) |
  749. ((dutcfg[12] & 0xC0) >> 1) |
  750. ((dutcfg[11] & 0xE0) >> 3) |
  751. ((dutcfg[6] & 0x80) >> 6) |
  752. ((dutcfg[1] & 0x80) >> 7);
  753. sw[2] = ((brdcfg[1] & 0x0f) << 4) |
  754. ((brdcfg[1] & 0x30) >> 2) |
  755. ((brdcfg[1] & 0x40) >> 5) |
  756. ((brdcfg[1] & 0x80) >> 7);
  757. sw[3] = brdcfg[2];
  758. sw[4] = ((dutcfg[2] & 0x01) << 7) |
  759. ((dutcfg[2] & 0x06) << 4) |
  760. ((~QIXIS_READ(present)) & 0x10) |
  761. ((brdcfg[3] & 0x80) >> 4) |
  762. ((brdcfg[3] & 0x01) << 2) |
  763. ((brdcfg[6] == 0x62) ? 3 :
  764. ((brdcfg[6] == 0x5a) ? 2 :
  765. ((brdcfg[6] == 0x5e) ? 1 : 0)));
  766. sw[5] = ((brdcfg[0] & 0x0f) << 4) |
  767. ((QIXIS_READ(rst_ctl) & 0x30) >> 2) |
  768. ((brdcfg[0] & 0x40) >> 5);
  769. sw[6] = (brdcfg[11] & 0x20) |
  770. ((brdcfg[5] & 0x02) << 3);
  771. sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) |
  772. ((brdcfg[5] & 0x10) << 2);
  773. sw[8] = ((brdcfg[12] & 0x08) << 4) |
  774. ((brdcfg[12] & 0x03) << 5);
  775. puts("DIP switch (reverse-engineering)\n");
  776. for (i = 0; i < 9; i++) {
  777. printf("SW%d = 0b%s (0x%02x)\n",
  778. i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
  779. }
  780. }
  781. static int do_vdd_adjust(cmd_tbl_t *cmdtp,
  782. int flag, int argc,
  783. char * const argv[])
  784. {
  785. ulong override;
  786. if (argc < 2)
  787. return CMD_RET_USAGE;
  788. if (!strict_strtoul(argv[1], 10, &override))
  789. adjust_vdd(override); /* the value is checked by callee */
  790. else
  791. return CMD_RET_USAGE;
  792. return 0;
  793. }
  794. U_BOOT_CMD(
  795. vdd_override, 2, 0, do_vdd_adjust,
  796. "Override VDD",
  797. "- override with the voltage specified in mV, eg. 1050"
  798. );