t208xqds.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2009-2013 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <env.h>
  8. #include <i2c.h>
  9. #include <init.h>
  10. #include <netdev.h>
  11. #include <linux/compiler.h>
  12. #include <asm/mmu.h>
  13. #include <asm/processor.h>
  14. #include <asm/immap_85xx.h>
  15. #include <asm/fsl_law.h>
  16. #include <asm/fsl_serdes.h>
  17. #include <asm/fsl_liodn.h>
  18. #include <fm_eth.h>
  19. #include "../common/qixis.h"
  20. #include "../common/vsc3316_3308.h"
  21. #include "../common/vid.h"
  22. #include "t208xqds.h"
  23. #include "t208xqds_qixis.h"
  24. DECLARE_GLOBAL_DATA_PTR;
  25. int checkboard(void)
  26. {
  27. char buf[64];
  28. u8 sw;
  29. struct cpu_type *cpu = gd->arch.cpu;
  30. static const char *freq[4] = {
  31. "100.00MHZ(from 8T49N222A)", "125.00MHz",
  32. "156.25MHZ", "100.00MHz"
  33. };
  34. printf("Board: %sQDS, ", cpu->name);
  35. sw = QIXIS_READ(arch);
  36. printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
  37. printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  38. #ifdef CONFIG_SDCARD
  39. puts("SD/MMC\n");
  40. #elif CONFIG_SPIFLASH
  41. puts("SPI\n");
  42. #else
  43. sw = QIXIS_READ(brdcfg[0]);
  44. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  45. if (sw < 0x8)
  46. printf("vBank%d\n", sw);
  47. else if (sw == 0x8)
  48. puts("Promjet\n");
  49. else if (sw == 0x9)
  50. puts("NAND\n");
  51. else
  52. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  53. #endif
  54. printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
  55. qixis_read_tag(buf), (int)qixis_read_minor());
  56. /* the timestamp string contains "\n" at the end */
  57. printf(" on %s", qixis_read_time(buf));
  58. puts("SERDES Reference Clocks:\n");
  59. sw = QIXIS_READ(brdcfg[2]);
  60. printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
  61. freq[(sw >> 4) & 0x3]);
  62. printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
  63. freq[sw & 0x3]);
  64. return 0;
  65. }
  66. int select_i2c_ch_pca9547(u8 ch)
  67. {
  68. int ret;
  69. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  70. if (ret) {
  71. puts("PCA: failed to select proper channel\n");
  72. return ret;
  73. }
  74. return 0;
  75. }
  76. int i2c_multiplexer_select_vid_channel(u8 channel)
  77. {
  78. return select_i2c_ch_pca9547(channel);
  79. }
  80. int brd_mux_lane_to_slot(void)
  81. {
  82. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  83. u32 srds_prtcl_s1;
  84. srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
  85. FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  86. srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  87. #if defined(CONFIG_TARGET_T2080QDS)
  88. u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
  89. FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
  90. srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
  91. #endif
  92. switch (srds_prtcl_s1) {
  93. case 0:
  94. /* SerDes1 is not enabled */
  95. break;
  96. #if defined(CONFIG_TARGET_T2080QDS)
  97. case 0x1b:
  98. case 0x1c:
  99. case 0xa2:
  100. /* SD1(A:D) => SLOT3 SGMII
  101. * SD1(G:H) => SLOT1 SGMII
  102. */
  103. QIXIS_WRITE(brdcfg[12], 0x1a);
  104. break;
  105. case 0x94:
  106. case 0x95:
  107. /* SD1(A:B) => SLOT3 SGMII@1.25bps
  108. * SD1(C:D) => SFP Module, SGMII@3.125bps
  109. * SD1(E:H) => SLOT1 SGMII@1.25bps
  110. */
  111. case 0x96:
  112. /* SD1(A:B) => SLOT3 SGMII@1.25bps
  113. * SD1(C) => SFP Module, SGMII@3.125bps
  114. * SD1(D) => SFP Module, SGMII@1.25bps
  115. * SD1(E:H) => SLOT1 PCIe4 x4
  116. */
  117. QIXIS_WRITE(brdcfg[12], 0x3a);
  118. break;
  119. case 0x50:
  120. case 0x51:
  121. /* SD1(A:D) => SLOT3 XAUI
  122. * SD1(E) => SLOT1 PCIe4
  123. * SD1(F:H) => SLOT2 SGMII
  124. */
  125. QIXIS_WRITE(brdcfg[12], 0x15);
  126. break;
  127. case 0x66:
  128. case 0x67:
  129. /* SD1(A:D) => XFI cage
  130. * SD1(E:H) => SLOT1 PCIe4
  131. */
  132. QIXIS_WRITE(brdcfg[12], 0xfe);
  133. break;
  134. case 0x6a:
  135. case 0x6b:
  136. /* SD1(A:D) => XFI cage
  137. * SD1(E) => SLOT1 PCIe4
  138. * SD1(F:H) => SLOT2 SGMII
  139. */
  140. QIXIS_WRITE(brdcfg[12], 0xf1);
  141. break;
  142. case 0x6c:
  143. case 0x6d:
  144. /* SD1(A:B) => XFI cage
  145. * SD1(C:D) => SLOT3 SGMII
  146. * SD1(E:H) => SLOT1 PCIe4
  147. */
  148. QIXIS_WRITE(brdcfg[12], 0xda);
  149. break;
  150. case 0x6e:
  151. /* SD1(A:B) => SFP Module, XFI
  152. * SD1(C:D) => SLOT3 SGMII
  153. * SD1(E:F) => SLOT1 PCIe4 x2
  154. * SD1(G:H) => SLOT2 SGMII
  155. */
  156. QIXIS_WRITE(brdcfg[12], 0xd9);
  157. break;
  158. case 0xda:
  159. /* SD1(A:H) => SLOT3 PCIe3 x8
  160. */
  161. QIXIS_WRITE(brdcfg[12], 0x0);
  162. break;
  163. case 0xc8:
  164. /* SD1(A) => SLOT3 PCIe3 x1
  165. * SD1(B) => SFP Module, SGMII@1.25bps
  166. * SD1(C:D) => SFP Module, SGMII@3.125bps
  167. * SD1(E:F) => SLOT1 PCIe4 x2
  168. * SD1(G:H) => SLOT2 SGMII
  169. */
  170. QIXIS_WRITE(brdcfg[12], 0x79);
  171. break;
  172. case 0xab:
  173. /* SD1(A:D) => SLOT3 PCIe3 x4
  174. * SD1(E:H) => SLOT1 PCIe4 x4
  175. */
  176. QIXIS_WRITE(brdcfg[12], 0x1a);
  177. break;
  178. #elif defined(CONFIG_TARGET_T2081QDS)
  179. case 0x50:
  180. case 0x51:
  181. /* SD1(A:D) => SLOT2 XAUI
  182. * SD1(E) => SLOT1 PCIe4 x1
  183. * SD1(F:H) => SLOT3 SGMII
  184. */
  185. QIXIS_WRITE(brdcfg[12], 0x98);
  186. QIXIS_WRITE(brdcfg[13], 0x70);
  187. break;
  188. case 0x6a:
  189. case 0x6b:
  190. /* SD1(A:D) => XFI SFP Module
  191. * SD1(E) => SLOT1 PCIe4 x1
  192. * SD1(F:H) => SLOT3 SGMII
  193. */
  194. QIXIS_WRITE(brdcfg[12], 0x80);
  195. QIXIS_WRITE(brdcfg[13], 0x70);
  196. break;
  197. case 0x6c:
  198. case 0x6d:
  199. /* SD1(A:B) => XFI SFP Module
  200. * SD1(C:D) => SLOT2 SGMII
  201. * SD1(E:H) => SLOT1 PCIe4 x4
  202. */
  203. QIXIS_WRITE(brdcfg[12], 0xe8);
  204. QIXIS_WRITE(brdcfg[13], 0x0);
  205. break;
  206. case 0xaa:
  207. case 0xab:
  208. /* SD1(A:D) => SLOT2 PCIe3 x4
  209. * SD1(F:H) => SLOT1 SGMI4 x4
  210. */
  211. QIXIS_WRITE(brdcfg[12], 0xf8);
  212. QIXIS_WRITE(brdcfg[13], 0x0);
  213. break;
  214. case 0xca:
  215. case 0xcb:
  216. /* SD1(A) => SLOT2 PCIe3 x1
  217. * SD1(B) => SLOT7 SGMII
  218. * SD1(C) => SLOT6 SGMII
  219. * SD1(D) => SLOT5 SGMII
  220. * SD1(E) => SLOT1 PCIe4 x1
  221. * SD1(F:H) => SLOT3 SGMII
  222. */
  223. QIXIS_WRITE(brdcfg[12], 0x80);
  224. QIXIS_WRITE(brdcfg[13], 0x70);
  225. break;
  226. case 0xde:
  227. case 0xdf:
  228. /* SD1(A:D) => SLOT2 PCIe3 x4
  229. * SD1(E) => SLOT1 PCIe4 x1
  230. * SD1(F) => SLOT4 PCIe1 x1
  231. * SD1(G) => SLOT3 PCIe2 x1
  232. * SD1(H) => SLOT7 SGMII
  233. */
  234. QIXIS_WRITE(brdcfg[12], 0x98);
  235. QIXIS_WRITE(brdcfg[13], 0x25);
  236. break;
  237. case 0xf2:
  238. /* SD1(A) => SLOT2 PCIe3 x1
  239. * SD1(B:D) => SLOT7 SGMII
  240. * SD1(E) => SLOT1 PCIe4 x1
  241. * SD1(F) => SLOT4 PCIe1 x1
  242. * SD1(G) => SLOT3 PCIe2 x1
  243. * SD1(H) => SLOT7 SGMII
  244. */
  245. QIXIS_WRITE(brdcfg[12], 0x81);
  246. QIXIS_WRITE(brdcfg[13], 0xa5);
  247. break;
  248. #endif
  249. default:
  250. printf("WARNING: unsupported for SerDes1 Protocol %d\n",
  251. srds_prtcl_s1);
  252. return -1;
  253. }
  254. #ifdef CONFIG_TARGET_T2080QDS
  255. switch (srds_prtcl_s2) {
  256. case 0:
  257. /* SerDes2 is not enabled */
  258. break;
  259. case 0x01:
  260. case 0x02:
  261. /* SD2(A:H) => SLOT4 PCIe1 */
  262. QIXIS_WRITE(brdcfg[13], 0x10);
  263. break;
  264. case 0x15:
  265. case 0x16:
  266. /*
  267. * SD2(A:D) => SLOT4 PCIe1
  268. * SD2(E:F) => SLOT5 PCIe2
  269. * SD2(G:H) => SATA1,SATA2
  270. */
  271. QIXIS_WRITE(brdcfg[13], 0xb0);
  272. break;
  273. case 0x18:
  274. /*
  275. * SD2(A:D) => SLOT4 PCIe1
  276. * SD2(E:F) => SLOT5 Aurora
  277. * SD2(G:H) => SATA1,SATA2
  278. */
  279. QIXIS_WRITE(brdcfg[13], 0x78);
  280. break;
  281. case 0x1f:
  282. /*
  283. * SD2(A:D) => SLOT4 PCIe1
  284. * SD2(E:H) => SLOT5 PCIe2
  285. */
  286. QIXIS_WRITE(brdcfg[13], 0xa0);
  287. break;
  288. case 0x29:
  289. case 0x2d:
  290. case 0x2e:
  291. /*
  292. * SD2(A:D) => SLOT4 SRIO2
  293. * SD2(E:H) => SLOT5 SRIO1
  294. */
  295. QIXIS_WRITE(brdcfg[13], 0xa0);
  296. break;
  297. case 0x36:
  298. /*
  299. * SD2(A:D) => SLOT4 SRIO2
  300. * SD2(E:F) => Aurora
  301. * SD2(G:H) => SATA1,SATA2
  302. */
  303. QIXIS_WRITE(brdcfg[13], 0x78);
  304. break;
  305. default:
  306. printf("WARNING: unsupported for SerDes2 Protocol %d\n",
  307. srds_prtcl_s2);
  308. return -1;
  309. }
  310. #endif
  311. return 0;
  312. }
  313. int board_early_init_r(void)
  314. {
  315. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  316. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  317. /*
  318. * Remap Boot flash + PROMJET region to caching-inhibited
  319. * so that flash can be erased properly.
  320. */
  321. /* Flush d-cache and invalidate i-cache of any FLASH data */
  322. flush_dcache();
  323. invalidate_icache();
  324. if (flash_esel == -1) {
  325. /* very unlikely unless something is messed up */
  326. puts("Error: Could not find TLB for FLASH BASE\n");
  327. flash_esel = 2; /* give our best effort to continue */
  328. } else {
  329. /* invalidate existing TLB entry for flash + promjet */
  330. disable_tlb(flash_esel);
  331. }
  332. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  333. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  334. 0, flash_esel, BOOKE_PAGESZ_256M, 1);
  335. /* Disable remote I2C connection to qixis fpga */
  336. QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
  337. /*
  338. * Adjust core voltage according to voltage ID
  339. * This function changes I2C mux to channel 2.
  340. */
  341. if (adjust_vdd(0))
  342. printf("Warning: Adjusting core voltage failed.\n");
  343. brd_mux_lane_to_slot();
  344. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  345. return 0;
  346. }
  347. unsigned long get_board_sys_clk(void)
  348. {
  349. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  350. #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
  351. /* use accurate clock measurement */
  352. int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
  353. int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
  354. u32 val;
  355. val = freq * base;
  356. if (val) {
  357. debug("SYS Clock measurement is: %d\n", val);
  358. return val;
  359. } else {
  360. printf("Warning: SYS clock measurement is invalid, ");
  361. printf("using value from brdcfg1.\n");
  362. }
  363. #endif
  364. switch (sysclk_conf & 0x0F) {
  365. case QIXIS_SYSCLK_83:
  366. return 83333333;
  367. case QIXIS_SYSCLK_100:
  368. return 100000000;
  369. case QIXIS_SYSCLK_125:
  370. return 125000000;
  371. case QIXIS_SYSCLK_133:
  372. return 133333333;
  373. case QIXIS_SYSCLK_150:
  374. return 150000000;
  375. case QIXIS_SYSCLK_160:
  376. return 160000000;
  377. case QIXIS_SYSCLK_166:
  378. return 166666666;
  379. }
  380. return 66666666;
  381. }
  382. unsigned long get_board_ddr_clk(void)
  383. {
  384. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  385. #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
  386. /* use accurate clock measurement */
  387. int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
  388. int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
  389. u32 val;
  390. val = freq * base;
  391. if (val) {
  392. debug("DDR Clock measurement is: %d\n", val);
  393. return val;
  394. } else {
  395. printf("Warning: DDR clock measurement is invalid, ");
  396. printf("using value from brdcfg1.\n");
  397. }
  398. #endif
  399. switch ((ddrclk_conf & 0x30) >> 4) {
  400. case QIXIS_DDRCLK_100:
  401. return 100000000;
  402. case QIXIS_DDRCLK_125:
  403. return 125000000;
  404. case QIXIS_DDRCLK_133:
  405. return 133333333;
  406. }
  407. return 66666666;
  408. }
  409. int misc_init_r(void)
  410. {
  411. return 0;
  412. }
  413. int ft_board_setup(void *blob, bd_t *bd)
  414. {
  415. phys_addr_t base;
  416. phys_size_t size;
  417. ft_cpu_setup(blob, bd);
  418. base = env_get_bootm_low();
  419. size = env_get_bootm_size();
  420. fdt_fixup_memory(blob, (u64)base, (u64)size);
  421. #ifdef CONFIG_PCI
  422. pci_of_setup(blob, bd);
  423. #endif
  424. fdt_fixup_liodn(blob);
  425. fsl_fdt_fixup_dr_usb(blob, bd);
  426. #ifdef CONFIG_SYS_DPAA_FMAN
  427. fdt_fixup_fman_ethernet(blob);
  428. fdt_fixup_board_enet(blob);
  429. #endif
  430. return 0;
  431. }