t104xrdb.c 3.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <env.h>
  8. #include <hwconfig.h>
  9. #include <init.h>
  10. #include <netdev.h>
  11. #include <linux/compiler.h>
  12. #include <asm/mmu.h>
  13. #include <asm/processor.h>
  14. #include <asm/cache.h>
  15. #include <asm/immap_85xx.h>
  16. #include <asm/fsl_fdt.h>
  17. #include <asm/fsl_law.h>
  18. #include <asm/fsl_serdes.h>
  19. #include <asm/fsl_liodn.h>
  20. #include <fm_eth.h>
  21. #include "../common/sleep.h"
  22. #include "t104xrdb.h"
  23. #include "cpld.h"
  24. DECLARE_GLOBAL_DATA_PTR;
  25. int checkboard(void)
  26. {
  27. struct cpu_type *cpu = gd->arch.cpu;
  28. u8 sw;
  29. #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
  30. printf("Board: %sD4RDB\n", cpu->name);
  31. #else
  32. printf("Board: %sRDB\n", cpu->name);
  33. #endif
  34. printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
  35. CPLD_READ(hw_ver), CPLD_READ(sw_ver));
  36. sw = CPLD_READ(flash_ctl_status);
  37. sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
  38. printf("vBank: %d\n", sw);
  39. return 0;
  40. }
  41. int board_early_init_f(void)
  42. {
  43. #if defined(CONFIG_DEEP_SLEEP)
  44. if (is_warm_boot())
  45. fsl_dp_disable_console();
  46. #endif
  47. return 0;
  48. }
  49. int board_early_init_r(void)
  50. {
  51. #ifdef CONFIG_SYS_FLASH_BASE
  52. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  53. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  54. /*
  55. * Remap Boot flash region to caching-inhibited
  56. * so that flash can be erased properly.
  57. */
  58. /* Flush d-cache and invalidate i-cache of any FLASH data */
  59. flush_dcache();
  60. invalidate_icache();
  61. if (flash_esel == -1) {
  62. /* very unlikely unless something is messed up */
  63. puts("Error: Could not find TLB for FLASH BASE\n");
  64. flash_esel = 2; /* give our best effort to continue */
  65. } else {
  66. /* invalidate existing TLB entry for flash */
  67. disable_tlb(flash_esel);
  68. }
  69. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  70. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  71. 0, flash_esel, BOOKE_PAGESZ_256M, 1);
  72. #endif
  73. return 0;
  74. }
  75. int misc_init_r(void)
  76. {
  77. ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  78. u32 srds_s1;
  79. srds_s1 = in_be32(&gur->rcwsr[4]) >> 24;
  80. printf("SERDES Reference : 0x%X\n", srds_s1);
  81. /* select SGMII*/
  82. if (srds_s1 == 0x86)
  83. CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
  84. MISC_CTL_SG_SEL);
  85. /* select SGMII and Aurora*/
  86. if (srds_s1 == 0x8E)
  87. CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
  88. MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL);
  89. #if defined(CONFIG_TARGET_T1040D4RDB)
  90. if (hwconfig("qe-tdm")) {
  91. CPLD_WRITE(sfp_ctl_status, CPLD_READ(sfp_ctl_status) |
  92. MISC_MUX_QE_TDM);
  93. printf("QECSR : 0x%02x, mux to qe-tdm\n",
  94. CPLD_READ(sfp_ctl_status));
  95. }
  96. /* Mask all CPLD interrupt sources, except QSGMII interrupts */
  97. if (CPLD_READ(sw_ver) < 0x03) {
  98. debug("CPLD SW version 0x%02x doesn't support int_mask\n",
  99. CPLD_READ(sw_ver));
  100. } else {
  101. CPLD_WRITE(int_mask, CPLD_INT_MASK_ALL &
  102. ~(CPLD_INT_MASK_QSGMII1 | CPLD_INT_MASK_QSGMII2));
  103. }
  104. #endif
  105. return 0;
  106. }
  107. int ft_board_setup(void *blob, bd_t *bd)
  108. {
  109. phys_addr_t base;
  110. phys_size_t size;
  111. ft_cpu_setup(blob, bd);
  112. base = env_get_bootm_low();
  113. size = env_get_bootm_size();
  114. fdt_fixup_memory(blob, (u64)base, (u64)size);
  115. #ifdef CONFIG_PCI
  116. pci_of_setup(blob, bd);
  117. #endif
  118. fdt_fixup_liodn(blob);
  119. #ifdef CONFIG_HAS_FSL_DR_USB
  120. fsl_fdt_fixup_dr_usb(blob, bd);
  121. #endif
  122. #ifdef CONFIG_SYS_DPAA_FMAN
  123. fdt_fixup_fman_ethernet(blob);
  124. #endif
  125. if (hwconfig("qe-tdm"))
  126. fdt_del_diu(blob);
  127. return 0;
  128. }