t102xrdb.c 7.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <env.h>
  8. #include <i2c.h>
  9. #include <init.h>
  10. #include <netdev.h>
  11. #include <linux/compiler.h>
  12. #include <asm/mmu.h>
  13. #include <asm/processor.h>
  14. #include <asm/immap_85xx.h>
  15. #include <asm/fsl_law.h>
  16. #include <asm/fsl_serdes.h>
  17. #include <asm/fsl_liodn.h>
  18. #include <fm_eth.h>
  19. #include "t102xrdb.h"
  20. #ifdef CONFIG_TARGET_T1024RDB
  21. #include "cpld.h"
  22. #elif defined(CONFIG_TARGET_T1023RDB)
  23. #include <i2c.h>
  24. #include <mmc.h>
  25. #endif
  26. #include "../common/sleep.h"
  27. DECLARE_GLOBAL_DATA_PTR;
  28. #ifdef CONFIG_TARGET_T1023RDB
  29. enum {
  30. GPIO1_SD_SEL = 0x00020000, /* GPIO1_14, 0: eMMC, 1:SD/MMC */
  31. GPIO1_EMMC_SEL,
  32. GPIO3_GET_VERSION, /* GPIO3_4/5, 00:RevB, 01: RevC */
  33. GPIO3_BRD_VER_MASK = 0x0c000000,
  34. GPIO3_OFFSET = 0x2000,
  35. I2C_GET_BANK,
  36. I2C_SET_BANK0,
  37. I2C_SET_BANK4,
  38. };
  39. #endif
  40. int checkboard(void)
  41. {
  42. struct cpu_type *cpu = gd->arch.cpu;
  43. static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
  44. ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  45. u32 srds_s1;
  46. srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  47. srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  48. printf("Board: %sRDB, ", cpu->name);
  49. #if defined(CONFIG_TARGET_T1024RDB)
  50. printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
  51. CPLD_READ(hw_ver), CPLD_READ(sw_ver));
  52. #elif defined(CONFIG_TARGET_T1023RDB)
  53. printf("Rev%c, ", t1023rdb_ctrl(GPIO3_GET_VERSION) + 'B');
  54. #endif
  55. printf("boot from ");
  56. #ifdef CONFIG_SDCARD
  57. puts("SD/MMC\n");
  58. #elif CONFIG_SPIFLASH
  59. puts("SPI\n");
  60. #elif defined(CONFIG_TARGET_T1024RDB)
  61. u8 reg;
  62. reg = CPLD_READ(flash_csr);
  63. if (reg & CPLD_BOOT_SEL) {
  64. puts("NAND\n");
  65. } else {
  66. reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
  67. printf("NOR vBank%d\n", reg);
  68. }
  69. #elif defined(CONFIG_TARGET_T1023RDB)
  70. #ifdef CONFIG_NAND
  71. puts("NAND\n");
  72. #else
  73. printf("NOR vBank%d\n", t1023rdb_ctrl(I2C_GET_BANK));
  74. #endif
  75. #endif
  76. puts("SERDES Reference Clocks:\n");
  77. if (srds_s1 == 0x95)
  78. printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
  79. else
  80. printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[1]);
  81. return 0;
  82. }
  83. #ifdef CONFIG_TARGET_T1024RDB
  84. static void board_mux_lane(void)
  85. {
  86. ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  87. u32 srds_prtcl_s1;
  88. u8 reg = CPLD_READ(misc_ctl_status);
  89. srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
  90. FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  91. srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  92. if (srds_prtcl_s1 == 0x95) {
  93. /* Route Lane B to PCIE */
  94. CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX);
  95. } else {
  96. /* Route Lane B to SGMII */
  97. CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX);
  98. }
  99. CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN);
  100. }
  101. #endif
  102. int board_early_init_f(void)
  103. {
  104. #if defined(CONFIG_DEEP_SLEEP)
  105. if (is_warm_boot())
  106. fsl_dp_disable_console();
  107. #endif
  108. return 0;
  109. }
  110. int board_early_init_r(void)
  111. {
  112. #ifdef CONFIG_SYS_FLASH_BASE
  113. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  114. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  115. /*
  116. * Remap Boot flash region to caching-inhibited
  117. * so that flash can be erased properly.
  118. */
  119. /* Flush d-cache and invalidate i-cache of any FLASH data */
  120. flush_dcache();
  121. invalidate_icache();
  122. if (flash_esel == -1) {
  123. /* very unlikely unless something is messed up */
  124. puts("Error: Could not find TLB for FLASH BASE\n");
  125. flash_esel = 2; /* give our best effort to continue */
  126. } else {
  127. /* invalidate existing TLB entry for flash + promjet */
  128. disable_tlb(flash_esel);
  129. }
  130. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  131. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  132. 0, flash_esel, BOOKE_PAGESZ_256M, 1);
  133. #endif
  134. #ifdef CONFIG_TARGET_T1024RDB
  135. board_mux_lane();
  136. #endif
  137. return 0;
  138. }
  139. unsigned long get_board_sys_clk(void)
  140. {
  141. return CONFIG_SYS_CLK_FREQ;
  142. }
  143. unsigned long get_board_ddr_clk(void)
  144. {
  145. return CONFIG_DDR_CLK_FREQ;
  146. }
  147. #ifdef CONFIG_TARGET_T1024RDB
  148. void board_reset(void)
  149. {
  150. CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
  151. }
  152. #endif
  153. int misc_init_r(void)
  154. {
  155. return 0;
  156. }
  157. int ft_board_setup(void *blob, bd_t *bd)
  158. {
  159. phys_addr_t base;
  160. phys_size_t size;
  161. ft_cpu_setup(blob, bd);
  162. base = env_get_bootm_low();
  163. size = env_get_bootm_size();
  164. fdt_fixup_memory(blob, (u64)base, (u64)size);
  165. #ifdef CONFIG_PCI
  166. pci_of_setup(blob, bd);
  167. #endif
  168. fdt_fixup_liodn(blob);
  169. fsl_fdt_fixup_dr_usb(blob, bd);
  170. #ifdef CONFIG_SYS_DPAA_FMAN
  171. fdt_fixup_fman_ethernet(blob);
  172. fdt_fixup_board_enet(blob);
  173. #endif
  174. #ifdef CONFIG_TARGET_T1023RDB
  175. if (t1023rdb_ctrl(GPIO3_GET_VERSION) > 0)
  176. fdt_enable_nor(blob);
  177. #endif
  178. return 0;
  179. }
  180. #ifdef CONFIG_TARGET_T1023RDB
  181. /* Enable NOR flash for RevC */
  182. static void fdt_enable_nor(void *blob)
  183. {
  184. int nodeoff = fdt_node_offset_by_compatible(blob, 0, "cfi-flash");
  185. if (nodeoff >= 0)
  186. fdt_status_okay(blob, nodeoff);
  187. else
  188. printf("WARNING unable to set status for NOR\n");
  189. }
  190. int board_mmc_getcd(struct mmc *mmc)
  191. {
  192. ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
  193. u32 val = in_be32(&pgpio->gpdat);
  194. /* GPIO1_14, 0: eMMC, 1: SD/MMC */
  195. val &= GPIO1_SD_SEL;
  196. return val ? -1 : 1;
  197. }
  198. int board_mmc_getwp(struct mmc *mmc)
  199. {
  200. ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
  201. u32 val = in_be32(&pgpio->gpdat);
  202. val &= GPIO1_SD_SEL;
  203. return val ? -1 : 0;
  204. }
  205. static u32 t1023rdb_ctrl(u32 ctrl_type)
  206. {
  207. ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
  208. ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  209. u32 val, orig_bus = i2c_get_bus_num();
  210. u8 tmp;
  211. switch (ctrl_type) {
  212. case GPIO1_SD_SEL:
  213. val = in_be32(&pgpio->gpdat);
  214. val |= GPIO1_SD_SEL;
  215. out_be32(&pgpio->gpdat, val);
  216. setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
  217. break;
  218. case GPIO1_EMMC_SEL:
  219. val = in_be32(&pgpio->gpdat);
  220. val &= ~GPIO1_SD_SEL;
  221. out_be32(&pgpio->gpdat, val);
  222. setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
  223. break;
  224. case GPIO3_GET_VERSION:
  225. pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
  226. + GPIO3_OFFSET);
  227. val = in_be32(&pgpio->gpdat);
  228. val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
  229. if (val == 0x3) /* GPIO3_4/5 not used on RevB */
  230. val = 0;
  231. return val;
  232. case I2C_GET_BANK:
  233. i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
  234. i2c_read(I2C_PCA6408_ADDR, 0, 1, &tmp, 1);
  235. tmp &= 0x7;
  236. tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2);
  237. i2c_set_bus_num(orig_bus);
  238. return tmp;
  239. case I2C_SET_BANK0:
  240. i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
  241. tmp = 0x0;
  242. i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
  243. tmp = 0xf8;
  244. i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
  245. /* asserting HRESET_REQ */
  246. out_be32(&gur->rstcr, 0x2);
  247. break;
  248. case I2C_SET_BANK4:
  249. i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
  250. tmp = 0x1;
  251. i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
  252. tmp = 0xf8;
  253. i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
  254. out_be32(&gur->rstcr, 0x2);
  255. break;
  256. default:
  257. break;
  258. }
  259. return 0;
  260. }
  261. static int switch_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
  262. char * const argv[])
  263. {
  264. if (argc < 2)
  265. return CMD_RET_USAGE;
  266. if (!strcmp(argv[1], "bank0"))
  267. t1023rdb_ctrl(I2C_SET_BANK0);
  268. else if (!strcmp(argv[1], "bank4") || !strcmp(argv[1], "altbank"))
  269. t1023rdb_ctrl(I2C_SET_BANK4);
  270. else if (!strcmp(argv[1], "sd"))
  271. t1023rdb_ctrl(GPIO1_SD_SEL);
  272. else if (!strcmp(argv[1], "emmc"))
  273. t1023rdb_ctrl(GPIO1_EMMC_SEL);
  274. else
  275. return CMD_RET_USAGE;
  276. return 0;
  277. }
  278. U_BOOT_CMD(
  279. switch, 2, 0, switch_cmd,
  280. "for bank0/bank4/sd/emmc switch control in runtime",
  281. "command (e.g. switch bank4)"
  282. );
  283. #endif