t102xqds.c 8.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <env.h>
  8. #include <i2c.h>
  9. #include <init.h>
  10. #include <netdev.h>
  11. #include <linux/compiler.h>
  12. #include <asm/mmu.h>
  13. #include <asm/processor.h>
  14. #include <asm/cache.h>
  15. #include <asm/immap_85xx.h>
  16. #include <asm/fsl_law.h>
  17. #include <asm/fsl_serdes.h>
  18. #include <asm/fsl_liodn.h>
  19. #include <fm_eth.h>
  20. #include <hwconfig.h>
  21. #include "../common/qixis.h"
  22. #include "t102xqds.h"
  23. #include "t102xqds_qixis.h"
  24. #include "../common/sleep.h"
  25. DECLARE_GLOBAL_DATA_PTR;
  26. int checkboard(void)
  27. {
  28. char buf[64];
  29. struct cpu_type *cpu = gd->arch.cpu;
  30. static const char *const freq[] = {"100", "125", "156.25", "100.0"};
  31. int clock;
  32. u8 sw = QIXIS_READ(arch);
  33. printf("Board: %sQDS, ", cpu->name);
  34. printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
  35. printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  36. #ifdef CONFIG_SDCARD
  37. puts("SD/MMC\n");
  38. #elif CONFIG_SPIFLASH
  39. puts("SPI\n");
  40. #else
  41. sw = QIXIS_READ(brdcfg[0]);
  42. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  43. if (sw < 0x8)
  44. printf("vBank: %d\n", sw);
  45. else if (sw == 0x8)
  46. puts("PromJet\n");
  47. else if (sw == 0x9)
  48. puts("NAND\n");
  49. else if (sw == 0x15)
  50. printf("IFC Card\n");
  51. else
  52. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  53. #endif
  54. printf("FPGA: v%d (%s), build %d",
  55. (int)QIXIS_READ(scver), qixis_read_tag(buf),
  56. (int)qixis_read_minor());
  57. /* the timestamp string contains "\n" at the end */
  58. printf(" on %s", qixis_read_time(buf));
  59. puts("SERDES Reference: ");
  60. sw = QIXIS_READ(brdcfg[2]);
  61. clock = (sw >> 6) & 3;
  62. printf("Clock1=%sMHz ", freq[clock]);
  63. clock = (sw >> 4) & 3;
  64. printf("Clock2=%sMHz\n", freq[clock]);
  65. return 0;
  66. }
  67. int select_i2c_ch_pca9547(u8 ch)
  68. {
  69. int ret;
  70. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  71. if (ret) {
  72. puts("PCA: failed to select proper channel\n");
  73. return ret;
  74. }
  75. return 0;
  76. }
  77. static int board_mux_lane_to_slot(void)
  78. {
  79. ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  80. u32 srds_prtcl_s1;
  81. u8 brdcfg9;
  82. srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
  83. FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  84. srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  85. brdcfg9 = QIXIS_READ(brdcfg[9]);
  86. QIXIS_WRITE(brdcfg[9], brdcfg9 | BRDCFG9_XFI_TX_DISABLE);
  87. switch (srds_prtcl_s1) {
  88. case 0:
  89. /* SerDes1 is not enabled */
  90. break;
  91. case 0xd5:
  92. case 0x5b:
  93. case 0x6b:
  94. case 0x77:
  95. case 0x6f:
  96. case 0x7f:
  97. QIXIS_WRITE(brdcfg[12], 0x8c);
  98. break;
  99. case 0x40:
  100. QIXIS_WRITE(brdcfg[12], 0xfc);
  101. break;
  102. case 0xd6:
  103. case 0x5a:
  104. case 0x6a:
  105. case 0x56:
  106. QIXIS_WRITE(brdcfg[12], 0x88);
  107. break;
  108. case 0x47:
  109. QIXIS_WRITE(brdcfg[12], 0xcc);
  110. break;
  111. case 0x46:
  112. QIXIS_WRITE(brdcfg[12], 0xc8);
  113. break;
  114. case 0x95:
  115. case 0x99:
  116. brdcfg9 &= ~BRDCFG9_XFI_TX_DISABLE;
  117. QIXIS_WRITE(brdcfg[9], brdcfg9);
  118. QIXIS_WRITE(brdcfg[12], 0x8c);
  119. break;
  120. case 0x116:
  121. QIXIS_WRITE(brdcfg[12], 0x00);
  122. break;
  123. case 0x115:
  124. case 0x119:
  125. case 0x129:
  126. case 0x12b:
  127. /* Aurora, PCIe, SGMII, SATA */
  128. QIXIS_WRITE(brdcfg[12], 0x04);
  129. break;
  130. default:
  131. printf("WARNING: unsupported for SerDes Protocol %d\n",
  132. srds_prtcl_s1);
  133. return -1;
  134. }
  135. return 0;
  136. }
  137. #ifdef CONFIG_ARCH_T1024
  138. static void board_mux_setup(void)
  139. {
  140. u8 brdcfg15;
  141. brdcfg15 = QIXIS_READ(brdcfg[15]);
  142. brdcfg15 &= ~BRDCFG15_DIUSEL_MASK;
  143. if (hwconfig_arg_cmp("pin_mux", "tdm")) {
  144. /* Route QE_TDM multiplexed signals to TDM Riser slot */
  145. QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_TDM);
  146. QIXIS_WRITE(brdcfg[13], BRDCFG13_TDM_INTERFACE << 2);
  147. QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
  148. ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_TDM);
  149. } else if (hwconfig_arg_cmp("pin_mux", "ucc")) {
  150. /* to UCC (ProfiBus) interface */
  151. QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_UCC);
  152. } else if (hwconfig_arg_cmp("pin_mux", "hdmi")) {
  153. /* to DVI (HDMI) encoder */
  154. QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_HDMI);
  155. } else if (hwconfig_arg_cmp("pin_mux", "lcd")) {
  156. /* to DFP (LCD) encoder */
  157. QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_LCDFM |
  158. BRDCFG15_LCDPD | BRDCFG15_DIUSEL_LCD);
  159. }
  160. if (hwconfig_arg_cmp("adaptor", "sdxc"))
  161. /* Route SPI_CS multiplexed signals to SD slot */
  162. QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
  163. ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_SDHC);
  164. }
  165. #endif
  166. void board_retimer_ds125df111_init(void)
  167. {
  168. u8 reg;
  169. /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */
  170. reg = I2C_MUX_CH7;
  171. i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &reg, 1);
  172. reg = I2C_MUX_CH5;
  173. i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
  174. /* Access to Control/Shared register */
  175. reg = 0x0;
  176. i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
  177. /* Read device revision and ID */
  178. i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
  179. debug("Retimer version id = 0x%x\n", reg);
  180. /* Enable Broadcast */
  181. reg = 0x0c;
  182. i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
  183. /* Reset Channel Registers */
  184. i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
  185. reg |= 0x4;
  186. i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
  187. /* Enable override divider select and Enable Override Output Mux */
  188. i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
  189. reg |= 0x24;
  190. i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
  191. /* Select VCO Divider to full rate (000) */
  192. i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
  193. reg &= 0x8f;
  194. i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
  195. /* Select active PFD MUX input as re-timed data (001) */
  196. i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
  197. reg &= 0x3f;
  198. reg |= 0x20;
  199. i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
  200. /* Set data rate as 10.3125 Gbps */
  201. reg = 0x0;
  202. i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
  203. reg = 0xb2;
  204. i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
  205. reg = 0x90;
  206. i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
  207. reg = 0xb3;
  208. i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
  209. reg = 0xcd;
  210. i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
  211. }
  212. int board_early_init_f(void)
  213. {
  214. #if defined(CONFIG_DEEP_SLEEP)
  215. if (is_warm_boot())
  216. fsl_dp_disable_console();
  217. #endif
  218. return 0;
  219. }
  220. int board_early_init_r(void)
  221. {
  222. #ifdef CONFIG_SYS_FLASH_BASE
  223. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  224. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  225. /*
  226. * Remap Boot flash + PROMJET region to caching-inhibited
  227. * so that flash can be erased properly.
  228. */
  229. /* Flush d-cache and invalidate i-cache of any FLASH data */
  230. flush_dcache();
  231. invalidate_icache();
  232. if (flash_esel == -1) {
  233. /* very unlikely unless something is messed up */
  234. puts("Error: Could not find TLB for FLASH BASE\n");
  235. flash_esel = 2; /* give our best effort to continue */
  236. } else {
  237. /* invalidate existing TLB entry for flash + promjet */
  238. disable_tlb(flash_esel);
  239. }
  240. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  241. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  242. 0, flash_esel, BOOKE_PAGESZ_256M, 1);
  243. #endif
  244. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  245. board_mux_lane_to_slot();
  246. board_retimer_ds125df111_init();
  247. /* Increase IO drive strength to address FCS error on RGMII */
  248. out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR, 0xbfdb7800);
  249. return 0;
  250. }
  251. unsigned long get_board_sys_clk(void)
  252. {
  253. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  254. switch (sysclk_conf & 0x0F) {
  255. case QIXIS_SYSCLK_64:
  256. return 64000000;
  257. case QIXIS_SYSCLK_83:
  258. return 83333333;
  259. case QIXIS_SYSCLK_100:
  260. return 100000000;
  261. case QIXIS_SYSCLK_125:
  262. return 125000000;
  263. case QIXIS_SYSCLK_133:
  264. return 133333333;
  265. case QIXIS_SYSCLK_150:
  266. return 150000000;
  267. case QIXIS_SYSCLK_160:
  268. return 160000000;
  269. case QIXIS_SYSCLK_166:
  270. return 166666666;
  271. }
  272. return 66666666;
  273. }
  274. unsigned long get_board_ddr_clk(void)
  275. {
  276. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  277. switch ((ddrclk_conf & 0x30) >> 4) {
  278. case QIXIS_DDRCLK_100:
  279. return 100000000;
  280. case QIXIS_DDRCLK_125:
  281. return 125000000;
  282. case QIXIS_DDRCLK_133:
  283. return 133333333;
  284. }
  285. return 66666666;
  286. }
  287. #define NUM_SRDS_PLL 2
  288. int misc_init_r(void)
  289. {
  290. #ifdef CONFIG_ARCH_T1024
  291. board_mux_setup();
  292. #endif
  293. return 0;
  294. }
  295. void fdt_fixup_spi_mux(void *blob)
  296. {
  297. int nodeoff = 0;
  298. if (hwconfig_arg_cmp("pin_mux", "tdm")) {
  299. while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
  300. "eon,en25s64")) >= 0) {
  301. fdt_del_node(blob, nodeoff);
  302. }
  303. } else {
  304. /* remove tdm node */
  305. while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
  306. "maxim,ds26522")) >= 0) {
  307. fdt_del_node(blob, nodeoff);
  308. }
  309. }
  310. }
  311. int ft_board_setup(void *blob, bd_t *bd)
  312. {
  313. phys_addr_t base;
  314. phys_size_t size;
  315. ft_cpu_setup(blob, bd);
  316. base = env_get_bootm_low();
  317. size = env_get_bootm_size();
  318. fdt_fixup_memory(blob, (u64)base, (u64)size);
  319. #ifdef CONFIG_PCI
  320. pci_of_setup(blob, bd);
  321. #endif
  322. fdt_fixup_liodn(blob);
  323. #ifdef CONFIG_HAS_FSL_DR_USB
  324. fsl_fdt_fixup_dr_usb(blob, bd);
  325. #endif
  326. #ifdef CONFIG_SYS_DPAA_FMAN
  327. fdt_fixup_fman_ethernet(blob);
  328. fdt_fixup_board_enet(blob);
  329. #endif
  330. fdt_fixup_spi_mux(blob);
  331. return 0;
  332. }
  333. void qixis_dump_switch(void)
  334. {
  335. int i, nr_of_cfgsw;
  336. QIXIS_WRITE(cms[0], 0x00);
  337. nr_of_cfgsw = QIXIS_READ(cms[1]);
  338. puts("DIP switch settings dump:\n");
  339. for (i = 1; i <= nr_of_cfgsw; i++) {
  340. QIXIS_WRITE(cms[0], i);
  341. printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
  342. }
  343. }