p2041rdb.c 5.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2011,2012 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <env.h>
  8. #include <init.h>
  9. #include <netdev.h>
  10. #include <linux/compiler.h>
  11. #include <asm/mmu.h>
  12. #include <asm/processor.h>
  13. #include <asm/cache.h>
  14. #include <asm/immap_85xx.h>
  15. #include <asm/fsl_law.h>
  16. #include <asm/fsl_serdes.h>
  17. #include <asm/fsl_liodn.h>
  18. #include <fm_eth.h>
  19. extern void pci_of_setup(void *blob, bd_t *bd);
  20. #include "cpld.h"
  21. DECLARE_GLOBAL_DATA_PTR;
  22. int checkboard(void)
  23. {
  24. u8 sw;
  25. struct cpu_type *cpu = gd->arch.cpu;
  26. unsigned int i;
  27. printf("Board: %sRDB, ", cpu->name);
  28. printf("CPLD version: %d.%d ", CPLD_READ(cpld_ver),
  29. CPLD_READ(cpld_ver_sub));
  30. sw = CPLD_READ(fbank_sel);
  31. printf("vBank: %d\n", sw & 0x1);
  32. /*
  33. * Display the actual SERDES reference clocks as configured by the
  34. * dip switches on the board. Note that the SWx registers could
  35. * technically be set to force the reference clocks to match the
  36. * values that the SERDES expects (or vice versa). For now, however,
  37. * we just display both values and hope the user notices when they
  38. * don't match.
  39. */
  40. puts("SERDES Reference Clocks: ");
  41. sw = in_8(&CPLD_SW(2)) >> 2;
  42. for (i = 0; i < 2; i++) {
  43. static const char * const freq[][3] = {{"0", "100", "125"},
  44. {"100", "156.25", "125"}
  45. };
  46. unsigned int clock = (sw >> (2 * i)) & 3;
  47. printf("Bank%u=%sMhz ", i+1, freq[i][clock]);
  48. }
  49. puts("\n");
  50. return 0;
  51. }
  52. int board_early_init_f(void)
  53. {
  54. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  55. /* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */
  56. setbits_be32(&gur->ddrclkdr, 0x000f000f);
  57. return 0;
  58. }
  59. #define CPLD_LANE_A_SEL 0x1
  60. #define CPLD_LANE_G_SEL 0x2
  61. #define CPLD_LANE_C_SEL 0x4
  62. #define CPLD_LANE_D_SEL 0x8
  63. void board_config_lanes_mux(void)
  64. {
  65. ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  66. int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
  67. FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
  68. u8 mux = 0;
  69. switch (srds_prtcl) {
  70. case 0x2:
  71. case 0x5:
  72. case 0x9:
  73. case 0xa:
  74. case 0xf:
  75. break;
  76. case 0x8:
  77. mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
  78. break;
  79. case 0x14:
  80. mux |= CPLD_LANE_A_SEL;
  81. break;
  82. case 0x17:
  83. mux |= CPLD_LANE_G_SEL;
  84. break;
  85. case 0x16:
  86. case 0x19:
  87. case 0x1a:
  88. mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
  89. break;
  90. case 0x1c:
  91. mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL;
  92. break;
  93. default:
  94. printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl);
  95. break;
  96. }
  97. CPLD_WRITE(serdes_mux, mux);
  98. }
  99. int board_early_init_r(void)
  100. {
  101. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  102. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  103. /*
  104. * Remap Boot flash + PROMJET region to caching-inhibited
  105. * so that flash can be erased properly.
  106. */
  107. /* Flush d-cache and invalidate i-cache of any FLASH data */
  108. flush_dcache();
  109. invalidate_icache();
  110. if (flash_esel == -1) {
  111. /* very unlikely unless something is messed up */
  112. puts("Error: Could not find TLB for FLASH BASE\n");
  113. flash_esel = 2; /* give our best effort to continue */
  114. } else {
  115. /* invalidate existing TLB entry for flash + promjet */
  116. disable_tlb(flash_esel);
  117. }
  118. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  119. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  120. 0, flash_esel, BOOKE_PAGESZ_256M, 1);
  121. board_config_lanes_mux();
  122. return 0;
  123. }
  124. unsigned long get_board_sys_clk(unsigned long dummy)
  125. {
  126. u8 sysclk_conf = CPLD_READ(sysclk_sw1);
  127. switch (sysclk_conf & 0x7) {
  128. case CPLD_SYSCLK_83:
  129. return 83333333;
  130. case CPLD_SYSCLK_100:
  131. return 100000000;
  132. default:
  133. return 66666666;
  134. }
  135. }
  136. #define NUM_SRDS_BANKS 2
  137. int misc_init_r(void)
  138. {
  139. serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  140. u32 actual[NUM_SRDS_BANKS];
  141. unsigned int i;
  142. u8 sw;
  143. static const int freq[][3] = {
  144. {0, SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_125},
  145. {SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_156_25,
  146. SRDS_PLLCR0_RFCK_SEL_125}
  147. };
  148. sw = in_8(&CPLD_SW(2)) >> 2;
  149. for (i = 0; i < NUM_SRDS_BANKS; i++) {
  150. unsigned int clock = (sw >> (2 * i)) & 3;
  151. if (clock == 0x3) {
  152. printf("Warning: SDREFCLK%u switch setting of '11' is "
  153. "unsupported\n", i + 1);
  154. break;
  155. }
  156. if (i == 0 && clock == 0)
  157. puts("Warning: SDREFCLK1 switch setting of"
  158. "'00' is unsupported\n");
  159. else
  160. actual[i] = freq[i][clock];
  161. /*
  162. * PC board uses a different CPLD with PB board, this CPLD
  163. * has cpld_ver_sub = 1, and pcba_ver = 5. But CPLD on PB
  164. * board has cpld_ver_sub = 0, and pcba_ver = 4.
  165. */
  166. if ((i == 1) && (CPLD_READ(cpld_ver_sub) == 1) &&
  167. (CPLD_READ(pcba_ver) == 5)) {
  168. /* PC board bank2 frequency */
  169. actual[i] = freq[i-1][clock];
  170. }
  171. }
  172. for (i = 0; i < NUM_SRDS_BANKS; i++) {
  173. u32 expected = in_be32(&regs->bank[i].pllcr0);
  174. expected &= SRDS_PLLCR0_RFCK_SEL_MASK;
  175. if (expected != actual[i]) {
  176. printf("Warning: SERDES bank %u expects reference clock"
  177. " %sMHz, but actual is %sMHz\n", i + 1,
  178. serdes_clock_to_string(expected),
  179. serdes_clock_to_string(actual[i]));
  180. }
  181. }
  182. return 0;
  183. }
  184. int ft_board_setup(void *blob, bd_t *bd)
  185. {
  186. phys_addr_t base;
  187. phys_size_t size;
  188. ft_cpu_setup(blob, bd);
  189. base = env_get_bootm_low();
  190. size = env_get_bootm_size();
  191. fdt_fixup_memory(blob, (u64)base, (u64)size);
  192. #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
  193. fsl_fdt_fixup_dr_usb(blob, bd);
  194. #endif
  195. #ifdef CONFIG_PCI
  196. pci_of_setup(blob, bd);
  197. #endif
  198. fdt_fixup_liodn(blob);
  199. #ifdef CONFIG_SYS_DPAA_FMAN
  200. fdt_fixup_fman_ethernet(blob);
  201. #endif
  202. return 0;
  203. }