p1022ds.c 8.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2010-2012 Freescale Semiconductor, Inc.
  4. * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
  5. * Timur Tabi <timur@freescale.com>
  6. */
  7. #include <common.h>
  8. #include <command.h>
  9. #include <env.h>
  10. #include <init.h>
  11. #include <pci.h>
  12. #include <asm/processor.h>
  13. #include <asm/mmu.h>
  14. #include <asm/cache.h>
  15. #include <asm/immap_85xx.h>
  16. #include <asm/fsl_pci.h>
  17. #include <fsl_ddr_sdram.h>
  18. #include <asm/fsl_serdes.h>
  19. #include <asm/io.h>
  20. #include <linux/libfdt.h>
  21. #include <fdt_support.h>
  22. #include <fsl_mdio.h>
  23. #include <tsec.h>
  24. #include <asm/fsl_law.h>
  25. #include <netdev.h>
  26. #include <i2c.h>
  27. #include <hwconfig.h>
  28. #include "../common/ngpixis.h"
  29. int board_early_init_f(void)
  30. {
  31. ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  32. /* Set pmuxcr to allow both i2c1 and i2c2 */
  33. setbits_be32(&gur->pmuxcr, 0x1000);
  34. #ifdef CONFIG_SYS_RAMBOOT
  35. setbits_be32(&gur->pmuxcr,
  36. in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
  37. #endif
  38. /* Read back the register to synchronize the write. */
  39. in_be32(&gur->pmuxcr);
  40. /* Set the pin muxing to enable ETSEC2. */
  41. clrbits_be32(&gur->pmuxcr2, 0x001F8000);
  42. /* Enable the SPI */
  43. clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI);
  44. return 0;
  45. }
  46. int checkboard(void)
  47. {
  48. u8 sw;
  49. printf("Board: P1022DS Sys ID: 0x%02x, "
  50. "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  51. in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
  52. sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
  53. switch ((sw & PIXIS_LBMAP_MASK) >> 6) {
  54. case 0:
  55. printf ("vBank: %u\n", ((sw & 0x30) >> 4));
  56. break;
  57. case 1:
  58. printf ("NAND\n");
  59. break;
  60. case 2:
  61. case 3:
  62. puts ("Promjet\n");
  63. break;
  64. }
  65. return 0;
  66. }
  67. #define CONFIG_TFP410_I2C_ADDR 0x38
  68. /* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */
  69. #define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK 0x0c
  70. #define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK 0x03
  71. /* Route the I2C1 pins to the SSI port instead. */
  72. #define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI 0x08
  73. /* Choose the 12.288Mhz codec reference clock */
  74. #define CONFIG_PIXIS_BRDCFG1_AUDCLK_12 0x02
  75. /* Choose the 11.2896Mhz codec reference clock */
  76. #define CONFIG_PIXIS_BRDCFG1_AUDCLK_11 0x01
  77. /* Connect to USB2 */
  78. #define CONFIG_PIXIS_BRDCFG0_USB2 0x10
  79. /* Connect to TFM bus */
  80. #define CONFIG_PIXIS_BRDCFG1_TDM 0x0c
  81. /* Connect to SPI */
  82. #define CONFIG_PIXIS_BRDCFG0_SPI 0x80
  83. int misc_init_r(void)
  84. {
  85. u8 temp;
  86. const char *audclk;
  87. size_t arglen;
  88. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  89. /* For DVI, enable the TFP410 Encoder. */
  90. temp = 0xBF;
  91. if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
  92. return -1;
  93. if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
  94. return -1;
  95. debug("DVI Encoder Read: 0x%02x\n", temp);
  96. temp = 0x10;
  97. if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
  98. return -1;
  99. if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
  100. return -1;
  101. debug("DVI Encoder Read: 0x%02x\n",temp);
  102. /* Enable the USB2 in PMUXCR2 and FGPA */
  103. if (hwconfig("usb2")) {
  104. clrsetbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_ETSECUSB_MASK,
  105. MPC85xx_PMUXCR2_USB);
  106. setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_USB2);
  107. }
  108. /* tdm and audio can not enable simultaneous*/
  109. if (hwconfig("tdm") && hwconfig("audclk")){
  110. printf("WARNING: TDM and AUDIO can not be enabled simultaneous !\n");
  111. return -1;
  112. }
  113. /* Enable the TDM in PMUXCR and FGPA */
  114. if (hwconfig("tdm")) {
  115. clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_MASK,
  116. MPC85xx_PMUXCR_TDM);
  117. setbits_8(&pixis->brdcfg1, CONFIG_PIXIS_BRDCFG1_TDM);
  118. /* TDM need some configration option by SPI */
  119. clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SPI_MASK,
  120. MPC85xx_PMUXCR_SPI);
  121. setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_SPI);
  122. }
  123. /*
  124. * Enable the reference clock for the WM8776 codec, and route the MUX
  125. * pins for SSI. The default is the 12.288 MHz clock
  126. */
  127. if (hwconfig("audclk")) {
  128. temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK |
  129. CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK);
  130. temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI;
  131. audclk = hwconfig_arg("audclk", &arglen);
  132. /* Check the first two chars only */
  133. if (audclk && (strncmp(audclk, "11", 2) == 0))
  134. temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11;
  135. else
  136. temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12;
  137. setbits_8(&pixis->brdcfg1, temp);
  138. }
  139. return 0;
  140. }
  141. /*
  142. * A list of PCI and SATA slots
  143. */
  144. enum slot_id {
  145. SLOT_PCIE1 = 1,
  146. SLOT_PCIE2,
  147. SLOT_PCIE3,
  148. SLOT_PCIE4,
  149. SLOT_PCIE5,
  150. SLOT_SATA1,
  151. SLOT_SATA2
  152. };
  153. /*
  154. * This array maps the slot identifiers to their names on the P1022DS board.
  155. */
  156. static const char *slot_names[] = {
  157. [SLOT_PCIE1] = "Slot 1",
  158. [SLOT_PCIE2] = "Slot 2",
  159. [SLOT_PCIE3] = "Slot 3",
  160. [SLOT_PCIE4] = "Slot 4",
  161. [SLOT_PCIE5] = "Mini-PCIe",
  162. [SLOT_SATA1] = "SATA 1",
  163. [SLOT_SATA2] = "SATA 2",
  164. };
  165. /*
  166. * This array maps a given SERDES configuration and SERDES device to the PCI or
  167. * SATA slot that it connects to. This mapping is hard-coded in the FPGA.
  168. */
  169. static u8 serdes_dev_slot[][SATA2 + 1] = {
  170. [0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
  171. [0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
  172. [0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
  173. [PCIE2] = SLOT_PCIE5 },
  174. [0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
  175. [PCIE2] = SLOT_PCIE3,
  176. [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
  177. [0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
  178. [PCIE2] = SLOT_PCIE3 },
  179. [0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
  180. [PCIE2] = SLOT_PCIE3,
  181. [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
  182. [0x1c] = { [PCIE1] = SLOT_PCIE1,
  183. [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
  184. [0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
  185. [0x1f] = { [PCIE1] = SLOT_PCIE1 },
  186. };
  187. /*
  188. * Returns the name of the slot to which the PCIe or SATA controller is
  189. * connected
  190. */
  191. const char *board_serdes_name(enum srds_prtcl device)
  192. {
  193. ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  194. u32 pordevsr = in_be32(&gur->pordevsr);
  195. unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
  196. MPC85xx_PORDEVSR_IO_SEL_SHIFT;
  197. enum slot_id slot = serdes_dev_slot[srds_cfg][device];
  198. const char *name = slot_names[slot];
  199. if (name)
  200. return name;
  201. else
  202. return "Nothing";
  203. }
  204. #ifdef CONFIG_PCI
  205. void pci_init_board(void)
  206. {
  207. fsl_pcie_init_board(0);
  208. }
  209. #endif
  210. int board_early_init_r(void)
  211. {
  212. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  213. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  214. /*
  215. * Remap Boot flash + PROMJET region to caching-inhibited
  216. * so that flash can be erased properly.
  217. */
  218. /* Flush d-cache and invalidate i-cache of any FLASH data */
  219. flush_dcache();
  220. invalidate_icache();
  221. if (flash_esel == -1) {
  222. /* very unlikely unless something is messed up */
  223. puts("Error: Could not find TLB for FLASH BASE\n");
  224. flash_esel = 2; /* give our best effort to continue */
  225. } else {
  226. /* invalidate existing TLB entry for flash + promjet */
  227. disable_tlb(flash_esel);
  228. }
  229. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  230. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  231. 0, flash_esel, BOOKE_PAGESZ_256M, 1);
  232. return 0;
  233. }
  234. /*
  235. * Initialize on-board and/or PCI Ethernet devices
  236. *
  237. * Returns:
  238. * <0, error
  239. * 0, no ethernet devices found
  240. * >0, number of ethernet devices initialized
  241. */
  242. int board_eth_init(bd_t *bis)
  243. {
  244. struct fsl_pq_mdio_info mdio_info;
  245. struct tsec_info_struct tsec_info[2];
  246. unsigned int num = 0;
  247. #ifdef CONFIG_TSEC1
  248. SET_STD_TSEC_INFO(tsec_info[num], 1);
  249. num++;
  250. #endif
  251. #ifdef CONFIG_TSEC2
  252. SET_STD_TSEC_INFO(tsec_info[num], 2);
  253. num++;
  254. #endif
  255. mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
  256. mdio_info.name = DEFAULT_MII_NAME;
  257. fsl_pq_mdio_init(bis, &mdio_info);
  258. return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
  259. }
  260. #ifdef CONFIG_OF_BOARD_SETUP
  261. /**
  262. * ft_codec_setup - fix up the clock-frequency property of the codec node
  263. *
  264. * Update the clock-frequency property based on the value of the 'audclk'
  265. * hwconfig option. If audclk is not specified, then don't write anything
  266. * to the device tree, because it means that the codec clock is disabled.
  267. */
  268. static void ft_codec_setup(void *blob, const char *compatible)
  269. {
  270. const char *audclk;
  271. size_t arglen;
  272. u32 freq;
  273. audclk = hwconfig_arg("audclk", &arglen);
  274. if (audclk) {
  275. if (strncmp(audclk, "11", 2) == 0)
  276. freq = 11289600;
  277. else
  278. freq = 12288000;
  279. do_fixup_by_compat_u32(blob, compatible, "clock-frequency",
  280. freq, 1);
  281. }
  282. }
  283. int ft_board_setup(void *blob, bd_t *bd)
  284. {
  285. phys_addr_t base;
  286. phys_size_t size;
  287. ft_cpu_setup(blob, bd);
  288. base = env_get_bootm_low();
  289. size = env_get_bootm_size();
  290. fdt_fixup_memory(blob, (u64)base, (u64)size);
  291. #ifdef CONFIG_HAS_FSL_DR_USB
  292. fsl_fdt_fixup_dr_usb(blob, bd);
  293. #endif
  294. FT_FSL_PCI_SETUP;
  295. #ifdef CONFIG_FSL_SGMII_RISER
  296. fsl_sgmii_riser_fdt_fixup(blob);
  297. #endif
  298. /* Update the WM8776 node's clock frequency property */
  299. ft_codec_setup(blob, "wlf,wm8776");
  300. return 0;
  301. }
  302. #endif