mx6sabreauto.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Freescale Semiconductor, Inc.
  4. *
  5. * Author: Fabio Estevam <fabio.estevam@freescale.com>
  6. */
  7. #include <common.h>
  8. #include <init.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/imx-regs.h>
  12. #include <asm/arch/iomux.h>
  13. #include <asm/arch/mx6-pins.h>
  14. #include <env.h>
  15. #include <linux/errno.h>
  16. #include <asm/gpio.h>
  17. #include <asm/mach-imx/iomux-v3.h>
  18. #include <asm/mach-imx/mxc_i2c.h>
  19. #include <asm/mach-imx/boot_mode.h>
  20. #include <asm/mach-imx/spi.h>
  21. #include <mmc.h>
  22. #include <fsl_esdhc_imx.h>
  23. #include <miiphy.h>
  24. #include <netdev.h>
  25. #include <asm/arch/sys_proto.h>
  26. #include <i2c.h>
  27. #include <input.h>
  28. #include <asm/arch/mxc_hdmi.h>
  29. #include <asm/mach-imx/video.h>
  30. #include <asm/arch/crm_regs.h>
  31. #include <pca953x.h>
  32. #include <power/pmic.h>
  33. #include <power/pfuze100_pmic.h>
  34. #include "../common/pfuze.h"
  35. DECLARE_GLOBAL_DATA_PTR;
  36. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  37. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  38. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  39. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  40. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  41. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  42. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  43. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  44. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  45. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  46. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  47. #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
  48. #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
  49. PAD_CTL_SRE_FAST)
  50. #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
  51. #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  52. #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  53. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  54. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  55. #define I2C_PMIC 1
  56. int dram_init(void)
  57. {
  58. gd->ram_size = imx_ddr_size();
  59. return 0;
  60. }
  61. static iomux_v3_cfg_t const uart4_pads[] = {
  62. IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  63. IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  64. };
  65. static iomux_v3_cfg_t const enet_pads[] = {
  66. IOMUX_PADS(PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  67. IOMUX_PADS(PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  68. IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  69. IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  70. IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  71. IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  72. IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  73. IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  74. IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  75. IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  76. IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  77. IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  78. IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  79. IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  80. IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  81. };
  82. /* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
  83. static struct i2c_pads_info mx6q_i2c_pad_info1 = {
  84. .scl = {
  85. .i2c_mode = MX6Q_PAD_EIM_EB2__I2C2_SCL | PC,
  86. .gpio_mode = MX6Q_PAD_EIM_EB2__GPIO2_IO30 | PC,
  87. .gp = IMX_GPIO_NR(2, 30)
  88. },
  89. .sda = {
  90. .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
  91. .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
  92. .gp = IMX_GPIO_NR(4, 13)
  93. }
  94. };
  95. static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
  96. .scl = {
  97. .i2c_mode = MX6DL_PAD_EIM_EB2__I2C2_SCL | PC,
  98. .gpio_mode = MX6DL_PAD_EIM_EB2__GPIO2_IO30 | PC,
  99. .gp = IMX_GPIO_NR(2, 30)
  100. },
  101. .sda = {
  102. .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
  103. .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
  104. .gp = IMX_GPIO_NR(4, 13)
  105. }
  106. };
  107. #ifndef CONFIG_SYS_FLASH_CFI
  108. /*
  109. * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
  110. * Compass Sensor, Accelerometer, Res Touch
  111. */
  112. static struct i2c_pads_info mx6q_i2c_pad_info2 = {
  113. .scl = {
  114. .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
  115. .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
  116. .gp = IMX_GPIO_NR(1, 3)
  117. },
  118. .sda = {
  119. .i2c_mode = MX6Q_PAD_EIM_D18__I2C3_SDA | PC,
  120. .gpio_mode = MX6Q_PAD_EIM_D18__GPIO3_IO18 | PC,
  121. .gp = IMX_GPIO_NR(3, 18)
  122. }
  123. };
  124. static struct i2c_pads_info mx6dl_i2c_pad_info2 = {
  125. .scl = {
  126. .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
  127. .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
  128. .gp = IMX_GPIO_NR(1, 3)
  129. },
  130. .sda = {
  131. .i2c_mode = MX6DL_PAD_EIM_D18__I2C3_SDA | PC,
  132. .gpio_mode = MX6DL_PAD_EIM_D18__GPIO3_IO18 | PC,
  133. .gp = IMX_GPIO_NR(3, 18)
  134. }
  135. };
  136. #endif
  137. static iomux_v3_cfg_t const i2c3_pads[] = {
  138. IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  139. };
  140. static iomux_v3_cfg_t const port_exp[] = {
  141. IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  142. };
  143. #ifdef CONFIG_MTD_NOR_FLASH
  144. static iomux_v3_cfg_t const eimnor_pads[] = {
  145. IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  146. IOMUX_PADS(PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  147. IOMUX_PADS(PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  148. IOMUX_PADS(PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  149. IOMUX_PADS(PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  150. IOMUX_PADS(PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  151. IOMUX_PADS(PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  152. IOMUX_PADS(PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  153. IOMUX_PADS(PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  154. IOMUX_PADS(PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  155. IOMUX_PADS(PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  156. IOMUX_PADS(PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  157. IOMUX_PADS(PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  158. IOMUX_PADS(PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  159. IOMUX_PADS(PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  160. IOMUX_PADS(PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  161. IOMUX_PADS(PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  162. IOMUX_PADS(PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  163. IOMUX_PADS(PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  164. IOMUX_PADS(PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  165. IOMUX_PADS(PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  166. IOMUX_PADS(PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  167. IOMUX_PADS(PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  168. IOMUX_PADS(PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  169. IOMUX_PADS(PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  170. IOMUX_PADS(PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  171. IOMUX_PADS(PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  172. IOMUX_PADS(PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  173. IOMUX_PADS(PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  174. IOMUX_PADS(PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  175. IOMUX_PADS(PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  176. IOMUX_PADS(PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  177. IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  178. IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  179. IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  180. IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  181. IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  182. IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  183. IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  184. IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  185. IOMUX_PADS(PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  186. IOMUX_PADS(PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL)),
  187. IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  188. };
  189. static void eimnor_cs_setup(void)
  190. {
  191. struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
  192. writel(0x00020181, &weim_regs->cs0gcr1);
  193. writel(0x00000001, &weim_regs->cs0gcr2);
  194. writel(0x0a020000, &weim_regs->cs0rcr1);
  195. writel(0x0000c000, &weim_regs->cs0rcr2);
  196. writel(0x0804a240, &weim_regs->cs0wcr1);
  197. writel(0x00000120, &weim_regs->wcr);
  198. set_chipselect_size(CS0_128);
  199. }
  200. static void eim_clk_setup(void)
  201. {
  202. struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  203. int cscmr1, ccgr6;
  204. /* Turn off EIM clock */
  205. ccgr6 = readl(&imx_ccm->CCGR6);
  206. ccgr6 &= ~(0x3 << 10);
  207. writel(ccgr6, &imx_ccm->CCGR6);
  208. /*
  209. * Configure clk_eim_slow_sel = 00 --> derive clock from AXI clk root
  210. * and aclk_eim_slow_podf = 01 --> divide by 2
  211. * so that we can have EIM at the maximum clock of 132MHz
  212. */
  213. cscmr1 = readl(&imx_ccm->cscmr1);
  214. cscmr1 &= ~(MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK |
  215. MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK);
  216. cscmr1 |= (1 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET);
  217. writel(cscmr1, &imx_ccm->cscmr1);
  218. /* Turn on EIM clock */
  219. ccgr6 |= (0x3 << 10);
  220. writel(ccgr6, &imx_ccm->CCGR6);
  221. }
  222. static void setup_iomux_eimnor(void)
  223. {
  224. SETUP_IOMUX_PADS(eimnor_pads);
  225. gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
  226. eimnor_cs_setup();
  227. }
  228. #endif
  229. static void setup_iomux_enet(void)
  230. {
  231. SETUP_IOMUX_PADS(enet_pads);
  232. }
  233. static iomux_v3_cfg_t const usdhc3_pads[] = {
  234. IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  235. IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  236. IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  237. IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  238. IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  239. IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  240. IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  241. IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  242. IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  243. IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  244. IOMUX_PADS(PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  245. IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  246. };
  247. static void setup_iomux_uart(void)
  248. {
  249. SETUP_IOMUX_PADS(uart4_pads);
  250. }
  251. #ifdef CONFIG_FSL_ESDHC_IMX
  252. static struct fsl_esdhc_cfg usdhc_cfg[1] = {
  253. {USDHC3_BASE_ADDR},
  254. };
  255. int board_mmc_getcd(struct mmc *mmc)
  256. {
  257. gpio_direction_input(IMX_GPIO_NR(6, 15));
  258. return !gpio_get_value(IMX_GPIO_NR(6, 15));
  259. }
  260. int board_mmc_init(bd_t *bis)
  261. {
  262. SETUP_IOMUX_PADS(usdhc3_pads);
  263. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  264. return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  265. }
  266. #endif
  267. #ifdef CONFIG_NAND_MXS
  268. static iomux_v3_cfg_t gpmi_pads[] = {
  269. IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  270. IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  271. IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  272. IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
  273. IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  274. IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  275. IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  276. IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  277. IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  278. IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  279. IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  280. IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  281. IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  282. IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  283. IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  284. IOMUX_PADS(PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL1)),
  285. };
  286. static void setup_gpmi_nand(void)
  287. {
  288. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  289. /* config gpmi nand iomux */
  290. SETUP_IOMUX_PADS(gpmi_pads);
  291. setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
  292. MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
  293. MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
  294. /* enable apbh clock gating */
  295. setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  296. }
  297. #endif
  298. static void setup_fec(void)
  299. {
  300. if (is_mx6dqp()) {
  301. /*
  302. * select ENET MAC0 TX clock from PLL
  303. */
  304. imx_iomux_set_gpr_register(5, 9, 1, 1);
  305. enable_fec_anatop_clock(0, ENET_125MHZ);
  306. }
  307. setup_iomux_enet();
  308. }
  309. int board_eth_init(bd_t *bis)
  310. {
  311. setup_fec();
  312. return cpu_eth_init(bis);
  313. }
  314. u32 get_board_rev(void)
  315. {
  316. int rev = nxp_board_rev();
  317. return (get_cpu_rev() & ~(0xF << 8)) | rev;
  318. }
  319. static int ar8031_phy_fixup(struct phy_device *phydev)
  320. {
  321. unsigned short val;
  322. /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
  323. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  324. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  325. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  326. val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
  327. val &= 0xffe3;
  328. val |= 0x18;
  329. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
  330. /* introduce tx clock delay */
  331. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
  332. val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
  333. val |= 0x0100;
  334. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
  335. return 0;
  336. }
  337. int board_phy_config(struct phy_device *phydev)
  338. {
  339. ar8031_phy_fixup(phydev);
  340. if (phydev->drv->config)
  341. phydev->drv->config(phydev);
  342. return 0;
  343. }
  344. #if defined(CONFIG_VIDEO_IPUV3)
  345. static void disable_lvds(struct display_info_t const *dev)
  346. {
  347. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  348. clrbits_le32(&iomux->gpr[2],
  349. IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
  350. IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
  351. }
  352. static void do_enable_hdmi(struct display_info_t const *dev)
  353. {
  354. disable_lvds(dev);
  355. imx_enable_hdmi_phy();
  356. }
  357. struct display_info_t const displays[] = {{
  358. .bus = -1,
  359. .addr = 0,
  360. .pixfmt = IPU_PIX_FMT_RGB666,
  361. .detect = NULL,
  362. .enable = NULL,
  363. .mode = {
  364. .name = "Hannstar-XGA",
  365. .refresh = 60,
  366. .xres = 1024,
  367. .yres = 768,
  368. .pixclock = 15385,
  369. .left_margin = 220,
  370. .right_margin = 40,
  371. .upper_margin = 21,
  372. .lower_margin = 7,
  373. .hsync_len = 60,
  374. .vsync_len = 10,
  375. .sync = FB_SYNC_EXT,
  376. .vmode = FB_VMODE_NONINTERLACED
  377. } }, {
  378. .bus = -1,
  379. .addr = 0,
  380. .pixfmt = IPU_PIX_FMT_RGB24,
  381. .detect = detect_hdmi,
  382. .enable = do_enable_hdmi,
  383. .mode = {
  384. .name = "HDMI",
  385. .refresh = 60,
  386. .xres = 1024,
  387. .yres = 768,
  388. .pixclock = 15385,
  389. .left_margin = 220,
  390. .right_margin = 40,
  391. .upper_margin = 21,
  392. .lower_margin = 7,
  393. .hsync_len = 60,
  394. .vsync_len = 10,
  395. .sync = FB_SYNC_EXT,
  396. .vmode = FB_VMODE_NONINTERLACED,
  397. } } };
  398. size_t display_count = ARRAY_SIZE(displays);
  399. iomux_v3_cfg_t const backlight_pads[] = {
  400. IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  401. };
  402. static void setup_iomux_backlight(void)
  403. {
  404. gpio_request(IMX_GPIO_NR(2, 9), "backlight");
  405. gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
  406. SETUP_IOMUX_PADS(backlight_pads);
  407. }
  408. static void setup_display(void)
  409. {
  410. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  411. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  412. int reg;
  413. setup_iomux_backlight();
  414. enable_ipu_clock();
  415. imx_setup_hdmi();
  416. /* Turn on LDB_DI0 and LDB_DI1 clocks */
  417. reg = readl(&mxc_ccm->CCGR3);
  418. reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
  419. writel(reg, &mxc_ccm->CCGR3);
  420. /* Set LDB_DI0 and LDB_DI1 clk select to 3b'011 */
  421. reg = readl(&mxc_ccm->cs2cdr);
  422. reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
  423. MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  424. reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
  425. (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  426. writel(reg, &mxc_ccm->cs2cdr);
  427. reg = readl(&mxc_ccm->cscmr2);
  428. reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
  429. writel(reg, &mxc_ccm->cscmr2);
  430. reg = readl(&mxc_ccm->chsccdr);
  431. reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  432. << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  433. reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
  434. MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
  435. writel(reg, &mxc_ccm->chsccdr);
  436. reg = IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
  437. IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
  438. IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
  439. IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
  440. IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
  441. IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
  442. IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
  443. IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED;
  444. writel(reg, &iomux->gpr[2]);
  445. reg = readl(&iomux->gpr[3]);
  446. reg &= ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
  447. IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
  448. reg |= (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
  449. IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
  450. (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
  451. IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET);
  452. writel(reg, &iomux->gpr[3]);
  453. }
  454. #endif /* CONFIG_VIDEO_IPUV3 */
  455. /*
  456. * Do not overwrite the console
  457. * Use always serial for U-Boot console
  458. */
  459. int overwrite_console(void)
  460. {
  461. return 1;
  462. }
  463. int board_early_init_f(void)
  464. {
  465. setup_iomux_uart();
  466. #ifdef CONFIG_NAND_MXS
  467. setup_gpmi_nand();
  468. #endif
  469. #ifdef CONFIG_MTD_NOR_FLASH
  470. eim_clk_setup();
  471. #endif
  472. return 0;
  473. }
  474. int board_init(void)
  475. {
  476. /* address of boot parameters */
  477. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  478. /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
  479. if (is_mx6dq() || is_mx6dqp())
  480. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
  481. else
  482. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
  483. /* I2C 3 Steer */
  484. gpio_request(IMX_GPIO_NR(5, 4), "steer logic");
  485. gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
  486. SETUP_IOMUX_PADS(i2c3_pads);
  487. #ifndef CONFIG_SYS_FLASH_CFI
  488. if (is_mx6dq() || is_mx6dqp())
  489. setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
  490. else
  491. setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
  492. #endif
  493. gpio_request(IMX_GPIO_NR(1, 15), "expander en");
  494. gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
  495. SETUP_IOMUX_PADS(port_exp);
  496. #ifdef CONFIG_VIDEO_IPUV3
  497. setup_display();
  498. #endif
  499. #ifdef CONFIG_MTD_NOR_FLASH
  500. setup_iomux_eimnor();
  501. #endif
  502. return 0;
  503. }
  504. #ifdef CONFIG_MXC_SPI
  505. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  506. {
  507. return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
  508. }
  509. #endif
  510. int power_init_board(void)
  511. {
  512. struct pmic *p;
  513. unsigned int value;
  514. p = pfuze_common_init(I2C_PMIC);
  515. if (!p)
  516. return -ENODEV;
  517. if (is_mx6dqp()) {
  518. /* set SW2 staby volatage 0.975V*/
  519. pmic_reg_read(p, PFUZE100_SW2STBY, &value);
  520. value &= ~0x3f;
  521. value |= 0x17;
  522. pmic_reg_write(p, PFUZE100_SW2STBY, value);
  523. }
  524. return pfuze_mode_init(p, APS_PFM);
  525. }
  526. #ifdef CONFIG_CMD_BMODE
  527. static const struct boot_mode board_boot_modes[] = {
  528. /* 4 bit bus width */
  529. {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  530. {NULL, 0},
  531. };
  532. #endif
  533. int board_late_init(void)
  534. {
  535. #ifdef CONFIG_CMD_BMODE
  536. add_board_boot_modes(board_boot_modes);
  537. #endif
  538. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  539. env_set("board_name", "SABREAUTO");
  540. if (is_mx6dqp())
  541. env_set("board_rev", "MX6QP");
  542. else if (is_mx6dq())
  543. env_set("board_rev", "MX6Q");
  544. else if (is_mx6sdl())
  545. env_set("board_rev", "MX6DL");
  546. #endif
  547. return 0;
  548. }
  549. int checkboard(void)
  550. {
  551. printf("Board: MX6Q-Sabreauto rev%c\n", nxp_board_rev_string());
  552. return 0;
  553. }
  554. #ifdef CONFIG_USB_EHCI_MX6
  555. int board_ehci_hcd_init(int port)
  556. {
  557. switch (port) {
  558. case 0:
  559. /*
  560. * Set daisy chain for otg_pin_id on 6q.
  561. * For 6dl, this bit is reserved.
  562. */
  563. imx_iomux_set_gpr_register(1, 13, 1, 0);
  564. break;
  565. case 1:
  566. break;
  567. default:
  568. printf("MXC USB port %d not yet supported\n", port);
  569. return -EINVAL;
  570. }
  571. return 0;
  572. }
  573. #endif
  574. #ifdef CONFIG_SPL_BUILD
  575. #include <asm/arch/mx6-ddr.h>
  576. #include <spl.h>
  577. #include <linux/libfdt.h>
  578. #ifdef CONFIG_SPL_OS_BOOT
  579. int spl_start_uboot(void)
  580. {
  581. return 0;
  582. }
  583. #endif
  584. static void ccgr_init(void)
  585. {
  586. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  587. writel(0x00C03F3F, &ccm->CCGR0);
  588. writel(0x0030FC03, &ccm->CCGR1);
  589. writel(0x0FFFC000, &ccm->CCGR2);
  590. writel(0x3FF00000, &ccm->CCGR3);
  591. writel(0x00FFF300, &ccm->CCGR4);
  592. writel(0x0F0000C3, &ccm->CCGR5);
  593. writel(0x000003FF, &ccm->CCGR6);
  594. }
  595. static int mx6q_dcd_table[] = {
  596. 0x020e0798, 0x000C0000,
  597. 0x020e0758, 0x00000000,
  598. 0x020e0588, 0x00000030,
  599. 0x020e0594, 0x00000030,
  600. 0x020e056c, 0x00000030,
  601. 0x020e0578, 0x00000030,
  602. 0x020e074c, 0x00000030,
  603. 0x020e057c, 0x00000030,
  604. 0x020e058c, 0x00000000,
  605. 0x020e059c, 0x00000030,
  606. 0x020e05a0, 0x00000030,
  607. 0x020e078c, 0x00000030,
  608. 0x020e0750, 0x00020000,
  609. 0x020e05a8, 0x00000028,
  610. 0x020e05b0, 0x00000028,
  611. 0x020e0524, 0x00000028,
  612. 0x020e051c, 0x00000028,
  613. 0x020e0518, 0x00000028,
  614. 0x020e050c, 0x00000028,
  615. 0x020e05b8, 0x00000028,
  616. 0x020e05c0, 0x00000028,
  617. 0x020e0774, 0x00020000,
  618. 0x020e0784, 0x00000028,
  619. 0x020e0788, 0x00000028,
  620. 0x020e0794, 0x00000028,
  621. 0x020e079c, 0x00000028,
  622. 0x020e07a0, 0x00000028,
  623. 0x020e07a4, 0x00000028,
  624. 0x020e07a8, 0x00000028,
  625. 0x020e0748, 0x00000028,
  626. 0x020e05ac, 0x00000028,
  627. 0x020e05b4, 0x00000028,
  628. 0x020e0528, 0x00000028,
  629. 0x020e0520, 0x00000028,
  630. 0x020e0514, 0x00000028,
  631. 0x020e0510, 0x00000028,
  632. 0x020e05bc, 0x00000028,
  633. 0x020e05c4, 0x00000028,
  634. 0x021b0800, 0xa1390003,
  635. 0x021b080c, 0x001F001F,
  636. 0x021b0810, 0x001F001F,
  637. 0x021b480c, 0x001F001F,
  638. 0x021b4810, 0x001F001F,
  639. 0x021b083c, 0x43260335,
  640. 0x021b0840, 0x031A030B,
  641. 0x021b483c, 0x4323033B,
  642. 0x021b4840, 0x0323026F,
  643. 0x021b0848, 0x483D4545,
  644. 0x021b4848, 0x44433E48,
  645. 0x021b0850, 0x41444840,
  646. 0x021b4850, 0x4835483E,
  647. 0x021b081c, 0x33333333,
  648. 0x021b0820, 0x33333333,
  649. 0x021b0824, 0x33333333,
  650. 0x021b0828, 0x33333333,
  651. 0x021b481c, 0x33333333,
  652. 0x021b4820, 0x33333333,
  653. 0x021b4824, 0x33333333,
  654. 0x021b4828, 0x33333333,
  655. 0x021b08b8, 0x00000800,
  656. 0x021b48b8, 0x00000800,
  657. 0x021b0004, 0x00020036,
  658. 0x021b0008, 0x09444040,
  659. 0x021b000c, 0x8A8F7955,
  660. 0x021b0010, 0xFF328F64,
  661. 0x021b0014, 0x01FF00DB,
  662. 0x021b0018, 0x00001740,
  663. 0x021b001c, 0x00008000,
  664. 0x021b002c, 0x000026d2,
  665. 0x021b0030, 0x008F1023,
  666. 0x021b0040, 0x00000047,
  667. 0x021b0000, 0x841A0000,
  668. 0x021b001c, 0x04088032,
  669. 0x021b001c, 0x00008033,
  670. 0x021b001c, 0x00048031,
  671. 0x021b001c, 0x09408030,
  672. 0x021b001c, 0x04008040,
  673. 0x021b0020, 0x00005800,
  674. 0x021b0818, 0x00011117,
  675. 0x021b4818, 0x00011117,
  676. 0x021b0004, 0x00025576,
  677. 0x021b0404, 0x00011006,
  678. 0x021b001c, 0x00000000,
  679. 0x020c4068, 0x00C03F3F,
  680. 0x020c406c, 0x0030FC03,
  681. 0x020c4070, 0x0FFFC000,
  682. 0x020c4074, 0x3FF00000,
  683. 0x020c4078, 0xFFFFF300,
  684. 0x020c407c, 0x0F0000F3,
  685. 0x020c4080, 0x00000FFF,
  686. 0x020e0010, 0xF00000CF,
  687. 0x020e0018, 0x007F007F,
  688. 0x020e001c, 0x007F007F,
  689. };
  690. static int mx6qp_dcd_table[] = {
  691. 0x020e0798, 0x000C0000,
  692. 0x020e0758, 0x00000000,
  693. 0x020e0588, 0x00000030,
  694. 0x020e0594, 0x00000030,
  695. 0x020e056c, 0x00000030,
  696. 0x020e0578, 0x00000030,
  697. 0x020e074c, 0x00000030,
  698. 0x020e057c, 0x00000030,
  699. 0x020e058c, 0x00000000,
  700. 0x020e059c, 0x00000030,
  701. 0x020e05a0, 0x00000030,
  702. 0x020e078c, 0x00000030,
  703. 0x020e0750, 0x00020000,
  704. 0x020e05a8, 0x00000030,
  705. 0x020e05b0, 0x00000030,
  706. 0x020e0524, 0x00000030,
  707. 0x020e051c, 0x00000030,
  708. 0x020e0518, 0x00000030,
  709. 0x020e050c, 0x00000030,
  710. 0x020e05b8, 0x00000030,
  711. 0x020e05c0, 0x00000030,
  712. 0x020e0774, 0x00020000,
  713. 0x020e0784, 0x00000030,
  714. 0x020e0788, 0x00000030,
  715. 0x020e0794, 0x00000030,
  716. 0x020e079c, 0x00000030,
  717. 0x020e07a0, 0x00000030,
  718. 0x020e07a4, 0x00000030,
  719. 0x020e07a8, 0x00000030,
  720. 0x020e0748, 0x00000030,
  721. 0x020e05ac, 0x00000030,
  722. 0x020e05b4, 0x00000030,
  723. 0x020e0528, 0x00000030,
  724. 0x020e0520, 0x00000030,
  725. 0x020e0514, 0x00000030,
  726. 0x020e0510, 0x00000030,
  727. 0x020e05bc, 0x00000030,
  728. 0x020e05c4, 0x00000030,
  729. 0x021b0800, 0xa1390003,
  730. 0x021b080c, 0x001b001e,
  731. 0x021b0810, 0x002e0029,
  732. 0x021b480c, 0x001b002a,
  733. 0x021b4810, 0x0019002c,
  734. 0x021b083c, 0x43240334,
  735. 0x021b0840, 0x0324031a,
  736. 0x021b483c, 0x43340344,
  737. 0x021b4840, 0x03280276,
  738. 0x021b0848, 0x44383A3E,
  739. 0x021b4848, 0x3C3C3846,
  740. 0x021b0850, 0x2e303230,
  741. 0x021b4850, 0x38283E34,
  742. 0x021b081c, 0x33333333,
  743. 0x021b0820, 0x33333333,
  744. 0x021b0824, 0x33333333,
  745. 0x021b0828, 0x33333333,
  746. 0x021b481c, 0x33333333,
  747. 0x021b4820, 0x33333333,
  748. 0x021b4824, 0x33333333,
  749. 0x021b4828, 0x33333333,
  750. 0x021b08c0, 0x24912492,
  751. 0x021b48c0, 0x24912492,
  752. 0x021b08b8, 0x00000800,
  753. 0x021b48b8, 0x00000800,
  754. 0x021b0004, 0x00020036,
  755. 0x021b0008, 0x09444040,
  756. 0x021b000c, 0x898E7955,
  757. 0x021b0010, 0xFF328F64,
  758. 0x021b0014, 0x01FF00DB,
  759. 0x021b0018, 0x00001740,
  760. 0x021b001c, 0x00008000,
  761. 0x021b002c, 0x000026d2,
  762. 0x021b0030, 0x008E1023,
  763. 0x021b0040, 0x00000047,
  764. 0x021b0400, 0x14420000,
  765. 0x021b0000, 0x841A0000,
  766. 0x00bb0008, 0x00000004,
  767. 0x00bb000c, 0x2891E41A,
  768. 0x00bb0038, 0x00000564,
  769. 0x00bb0014, 0x00000040,
  770. 0x00bb0028, 0x00000020,
  771. 0x00bb002c, 0x00000020,
  772. 0x021b001c, 0x04088032,
  773. 0x021b001c, 0x00008033,
  774. 0x021b001c, 0x00048031,
  775. 0x021b001c, 0x09408030,
  776. 0x021b001c, 0x04008040,
  777. 0x021b0020, 0x00005800,
  778. 0x021b0818, 0x00011117,
  779. 0x021b4818, 0x00011117,
  780. 0x021b0004, 0x00025576,
  781. 0x021b0404, 0x00011006,
  782. 0x021b001c, 0x00000000,
  783. 0x020c4068, 0x00C03F3F,
  784. 0x020c406c, 0x0030FC03,
  785. 0x020c4070, 0x0FFFC000,
  786. 0x020c4074, 0x3FF00000,
  787. 0x020c4078, 0xFFFFF300,
  788. 0x020c407c, 0x0F0000F3,
  789. 0x020c4080, 0x00000FFF,
  790. 0x020e0010, 0xF00000CF,
  791. 0x020e0018, 0x77177717,
  792. 0x020e001c, 0x77177717,
  793. };
  794. static int mx6dl_dcd_table[] = {
  795. 0x020e0774, 0x000C0000,
  796. 0x020e0754, 0x00000000,
  797. 0x020e04ac, 0x00000030,
  798. 0x020e04b0, 0x00000030,
  799. 0x020e0464, 0x00000030,
  800. 0x020e0490, 0x00000030,
  801. 0x020e074c, 0x00000030,
  802. 0x020e0494, 0x00000030,
  803. 0x020e04a0, 0x00000000,
  804. 0x020e04b4, 0x00000030,
  805. 0x020e04b8, 0x00000030,
  806. 0x020e076c, 0x00000030,
  807. 0x020e0750, 0x00020000,
  808. 0x020e04bc, 0x00000028,
  809. 0x020e04c0, 0x00000028,
  810. 0x020e04c4, 0x00000028,
  811. 0x020e04c8, 0x00000028,
  812. 0x020e04cc, 0x00000028,
  813. 0x020e04d0, 0x00000028,
  814. 0x020e04d4, 0x00000028,
  815. 0x020e04d8, 0x00000028,
  816. 0x020e0760, 0x00020000,
  817. 0x020e0764, 0x00000028,
  818. 0x020e0770, 0x00000028,
  819. 0x020e0778, 0x00000028,
  820. 0x020e077c, 0x00000028,
  821. 0x020e0780, 0x00000028,
  822. 0x020e0784, 0x00000028,
  823. 0x020e078c, 0x00000028,
  824. 0x020e0748, 0x00000028,
  825. 0x020e0470, 0x00000028,
  826. 0x020e0474, 0x00000028,
  827. 0x020e0478, 0x00000028,
  828. 0x020e047c, 0x00000028,
  829. 0x020e0480, 0x00000028,
  830. 0x020e0484, 0x00000028,
  831. 0x020e0488, 0x00000028,
  832. 0x020e048c, 0x00000028,
  833. 0x021b0800, 0xa1390003,
  834. 0x021b080c, 0x001F001F,
  835. 0x021b0810, 0x001F001F,
  836. 0x021b480c, 0x001F001F,
  837. 0x021b4810, 0x001F001F,
  838. 0x021b083c, 0x42190217,
  839. 0x021b0840, 0x017B017B,
  840. 0x021b483c, 0x4176017B,
  841. 0x021b4840, 0x015F016C,
  842. 0x021b0848, 0x4C4C4D4C,
  843. 0x021b4848, 0x4A4D4C48,
  844. 0x021b0850, 0x3F3F3F40,
  845. 0x021b4850, 0x3538382E,
  846. 0x021b081c, 0x33333333,
  847. 0x021b0820, 0x33333333,
  848. 0x021b0824, 0x33333333,
  849. 0x021b0828, 0x33333333,
  850. 0x021b481c, 0x33333333,
  851. 0x021b4820, 0x33333333,
  852. 0x021b4824, 0x33333333,
  853. 0x021b4828, 0x33333333,
  854. 0x021b08b8, 0x00000800,
  855. 0x021b48b8, 0x00000800,
  856. 0x021b0004, 0x00020025,
  857. 0x021b0008, 0x00333030,
  858. 0x021b000c, 0x676B5313,
  859. 0x021b0010, 0xB66E8B63,
  860. 0x021b0014, 0x01FF00DB,
  861. 0x021b0018, 0x00001740,
  862. 0x021b001c, 0x00008000,
  863. 0x021b002c, 0x000026d2,
  864. 0x021b0030, 0x006B1023,
  865. 0x021b0040, 0x00000047,
  866. 0x021b0000, 0x841A0000,
  867. 0x021b001c, 0x04008032,
  868. 0x021b001c, 0x00008033,
  869. 0x021b001c, 0x00048031,
  870. 0x021b001c, 0x05208030,
  871. 0x021b001c, 0x04008040,
  872. 0x021b0020, 0x00005800,
  873. 0x021b0818, 0x00011117,
  874. 0x021b4818, 0x00011117,
  875. 0x021b0004, 0x00025565,
  876. 0x021b0404, 0x00011006,
  877. 0x021b001c, 0x00000000,
  878. 0x020c4068, 0x00C03F3F,
  879. 0x020c406c, 0x0030FC03,
  880. 0x020c4070, 0x0FFFC000,
  881. 0x020c4074, 0x3FF00000,
  882. 0x020c4078, 0xFFFFF300,
  883. 0x020c407c, 0x0F0000C3,
  884. 0x020c4080, 0x00000FFF,
  885. 0x020e0010, 0xF00000CF,
  886. 0x020e0018, 0x007F007F,
  887. 0x020e001c, 0x007F007F,
  888. };
  889. static void ddr_init(int *table, int size)
  890. {
  891. int i;
  892. for (i = 0; i < size / 2 ; i++)
  893. writel(table[2 * i + 1], table[2 * i]);
  894. }
  895. static void spl_dram_init(void)
  896. {
  897. if (is_mx6dq())
  898. ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
  899. else if (is_mx6dqp())
  900. ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
  901. else if (is_mx6sdl())
  902. ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
  903. }
  904. void board_init_f(ulong dummy)
  905. {
  906. /* DDR initialization */
  907. spl_dram_init();
  908. /* setup AIPS and disable watchdog */
  909. arch_cpu_init();
  910. ccgr_init();
  911. gpr_init();
  912. /* iomux and setup of i2c */
  913. board_early_init_f();
  914. /* setup GP timer */
  915. timer_init();
  916. /* UART clocks enabled and gd valid - init serial console */
  917. preloader_console_init();
  918. /* Clear the BSS. */
  919. memset(__bss_start, 0, __bss_end - __bss_start);
  920. /* load/boot image from boot device */
  921. board_init_r(NULL, 0);
  922. }
  923. #endif
  924. #ifdef CONFIG_SPL_LOAD_FIT
  925. int board_fit_config_name_match(const char *name)
  926. {
  927. if (is_mx6dq()) {
  928. if (!strcmp(name, "imx6q-sabreauto"))
  929. return 0;
  930. } else if (is_mx6dqp()) {
  931. if (!strcmp(name, "imx6qp-sabreauto"))
  932. return 0;
  933. } else if (is_mx6dl()) {
  934. if (!strcmp(name, "imx6dl-sabreauto"))
  935. return 0;
  936. }
  937. return -1;
  938. }
  939. #endif