mx53loco.c 9.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2011 Freescale Semiconductor, Inc.
  4. * Jason Liu <r64343@freescale.com>
  5. */
  6. #include <common.h>
  7. #include <init.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/imx-regs.h>
  10. #include <asm/arch/sys_proto.h>
  11. #include <asm/arch/crm_regs.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch/iomux-mx53.h>
  14. #include <asm/arch/clock.h>
  15. #include <env.h>
  16. #include <linux/errno.h>
  17. #include <asm/mach-imx/mx5_video.h>
  18. #include <netdev.h>
  19. #include <i2c.h>
  20. #include <input.h>
  21. #include <mmc.h>
  22. #include <fsl_esdhc_imx.h>
  23. #include <asm/gpio.h>
  24. #include <power/pmic.h>
  25. #include <dialog_pmic.h>
  26. #include <fsl_pmic.h>
  27. #include <linux/fb.h>
  28. #include <ipu_pixfmt.h>
  29. #define MX53LOCO_LCD_POWER IMX_GPIO_NR(3, 24)
  30. DECLARE_GLOBAL_DATA_PTR;
  31. u32 get_board_rev(void)
  32. {
  33. struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
  34. struct fuse_bank *bank = &iim->bank[0];
  35. struct fuse_bank0_regs *fuse =
  36. (struct fuse_bank0_regs *)bank->fuse_regs;
  37. int rev = readl(&fuse->gp[6]);
  38. if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR))
  39. rev = 0;
  40. return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
  41. }
  42. #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
  43. PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
  44. static void setup_iomux_uart(void)
  45. {
  46. static const iomux_v3_cfg_t uart_pads[] = {
  47. NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
  48. NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
  49. };
  50. imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  51. }
  52. #ifdef CONFIG_USB_EHCI_MX5
  53. int board_ehci_hcd_init(int port)
  54. {
  55. /* request VBUS power enable pin, GPIO7_8 */
  56. imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8);
  57. gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
  58. return 0;
  59. }
  60. #endif
  61. static void setup_iomux_fec(void)
  62. {
  63. static const iomux_v3_cfg_t fec_pads[] = {
  64. NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
  65. PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
  66. NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
  67. NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
  68. PAD_CTL_HYS | PAD_CTL_PKE),
  69. NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
  70. PAD_CTL_HYS | PAD_CTL_PKE),
  71. NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
  72. NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
  73. NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
  74. NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
  75. PAD_CTL_HYS | PAD_CTL_PKE),
  76. NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
  77. PAD_CTL_HYS | PAD_CTL_PKE),
  78. NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
  79. PAD_CTL_HYS | PAD_CTL_PKE),
  80. };
  81. imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
  82. }
  83. #ifdef CONFIG_FSL_ESDHC_IMX
  84. struct fsl_esdhc_cfg esdhc_cfg[2] = {
  85. {MMC_SDHC1_BASE_ADDR},
  86. {MMC_SDHC3_BASE_ADDR},
  87. };
  88. int board_mmc_getcd(struct mmc *mmc)
  89. {
  90. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  91. int ret;
  92. imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11);
  93. gpio_direction_input(IMX_GPIO_NR(3, 11));
  94. imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
  95. gpio_direction_input(IMX_GPIO_NR(3, 13));
  96. if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
  97. ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
  98. else
  99. ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
  100. return ret;
  101. }
  102. #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
  103. PAD_CTL_PUS_100K_UP)
  104. #define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
  105. PAD_CTL_DSE_HIGH)
  106. int board_mmc_init(bd_t *bis)
  107. {
  108. static const iomux_v3_cfg_t sd1_pads[] = {
  109. NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
  110. NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
  111. NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
  112. NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
  113. NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
  114. NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
  115. MX53_PAD_EIM_DA13__GPIO3_13,
  116. };
  117. static const iomux_v3_cfg_t sd2_pads[] = {
  118. NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
  119. SD_CMD_PAD_CTRL),
  120. NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
  121. NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
  122. NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
  123. NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
  124. NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
  125. NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
  126. NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
  127. NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
  128. NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
  129. MX53_PAD_EIM_DA11__GPIO3_11,
  130. };
  131. u32 index;
  132. int ret;
  133. esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  134. esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  135. for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
  136. switch (index) {
  137. case 0:
  138. imx_iomux_v3_setup_multiple_pads(sd1_pads,
  139. ARRAY_SIZE(sd1_pads));
  140. break;
  141. case 1:
  142. imx_iomux_v3_setup_multiple_pads(sd2_pads,
  143. ARRAY_SIZE(sd2_pads));
  144. break;
  145. default:
  146. printf("Warning: you configured more ESDHC controller"
  147. "(%d) as supported by the board(2)\n",
  148. CONFIG_SYS_FSL_ESDHC_NUM);
  149. return -EINVAL;
  150. }
  151. ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
  152. if (ret)
  153. return ret;
  154. }
  155. return 0;
  156. }
  157. #endif
  158. #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
  159. PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
  160. static void setup_iomux_i2c(void)
  161. {
  162. static const iomux_v3_cfg_t i2c1_pads[] = {
  163. NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
  164. NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
  165. };
  166. imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
  167. }
  168. static int power_init(void)
  169. {
  170. unsigned int val;
  171. int ret;
  172. struct pmic *p;
  173. if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
  174. ret = pmic_dialog_init(I2C_PMIC);
  175. if (ret)
  176. return ret;
  177. p = pmic_get("DIALOG_PMIC");
  178. if (!p)
  179. return -ENODEV;
  180. env_set("fdt_file", "imx53-qsb.dtb");
  181. /* Set VDDA to 1.25V */
  182. val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
  183. ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
  184. if (ret) {
  185. printf("Writing to BUCKCORE_REG failed: %d\n", ret);
  186. return ret;
  187. }
  188. pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
  189. val |= DA9052_SUPPLY_VBCOREGO;
  190. ret = pmic_reg_write(p, DA9053_SUPPLY_REG, val);
  191. if (ret) {
  192. printf("Writing to SUPPLY_REG failed: %d\n", ret);
  193. return ret;
  194. }
  195. /* Set Vcc peripheral to 1.30V */
  196. ret = pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
  197. if (ret) {
  198. printf("Writing to BUCKPRO_REG failed: %d\n", ret);
  199. return ret;
  200. }
  201. ret = pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
  202. if (ret) {
  203. printf("Writing to SUPPLY_REG failed: %d\n", ret);
  204. return ret;
  205. }
  206. return ret;
  207. }
  208. if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
  209. ret = pmic_init(I2C_0);
  210. if (ret)
  211. return ret;
  212. p = pmic_get("FSL_PMIC");
  213. if (!p)
  214. return -ENODEV;
  215. env_set("fdt_file", "imx53-qsrb.dtb");
  216. /* Set VDDGP to 1.25V for 1GHz on SW1 */
  217. pmic_reg_read(p, REG_SW_0, &val);
  218. val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
  219. ret = pmic_reg_write(p, REG_SW_0, val);
  220. if (ret) {
  221. printf("Writing to REG_SW_0 failed: %d\n", ret);
  222. return ret;
  223. }
  224. /* Set VCC as 1.30V on SW2 */
  225. pmic_reg_read(p, REG_SW_1, &val);
  226. val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
  227. ret = pmic_reg_write(p, REG_SW_1, val);
  228. if (ret) {
  229. printf("Writing to REG_SW_1 failed: %d\n", ret);
  230. return ret;
  231. }
  232. /* Set global reset timer to 4s */
  233. pmic_reg_read(p, REG_POWER_CTL2, &val);
  234. val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
  235. ret = pmic_reg_write(p, REG_POWER_CTL2, val);
  236. if (ret) {
  237. printf("Writing to REG_POWER_CTL2 failed: %d\n", ret);
  238. return ret;
  239. }
  240. /* Set VUSBSEL and VUSBEN for USB PHY supply*/
  241. pmic_reg_read(p, REG_MODE_0, &val);
  242. val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
  243. ret = pmic_reg_write(p, REG_MODE_0, val);
  244. if (ret) {
  245. printf("Writing to REG_MODE_0 failed: %d\n", ret);
  246. return ret;
  247. }
  248. /* Set SWBST to 5V in auto mode */
  249. val = SWBST_AUTO;
  250. ret = pmic_reg_write(p, SWBST_CTRL, val);
  251. if (ret) {
  252. printf("Writing to SWBST_CTRL failed: %d\n", ret);
  253. return ret;
  254. }
  255. return ret;
  256. }
  257. return -1;
  258. }
  259. static void clock_1GHz(void)
  260. {
  261. int ret;
  262. u32 ref_clk = MXC_HCLK;
  263. /*
  264. * After increasing voltage to 1.25V, we can switch
  265. * CPU clock to 1GHz and DDR to 400MHz safely
  266. */
  267. ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
  268. if (ret)
  269. printf("CPU: Switch CPU clock to 1GHZ failed\n");
  270. ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
  271. ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
  272. if (ret)
  273. printf("CPU: Switch DDR clock to 400MHz failed\n");
  274. }
  275. int board_early_init_f(void)
  276. {
  277. setup_iomux_uart();
  278. setup_iomux_fec();
  279. setup_iomux_lcd();
  280. return 0;
  281. }
  282. /*
  283. * Do not overwrite the console
  284. * Use always serial for U-Boot console
  285. */
  286. int overwrite_console(void)
  287. {
  288. return 1;
  289. }
  290. int board_init(void)
  291. {
  292. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  293. mxc_set_sata_internal_clock();
  294. setup_iomux_i2c();
  295. return 0;
  296. }
  297. int board_late_init(void)
  298. {
  299. if (!power_init())
  300. clock_1GHz();
  301. return 0;
  302. }
  303. int checkboard(void)
  304. {
  305. puts("Board: MX53 LOCO\n");
  306. return 0;
  307. }