mpc8572ds.c 5.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007-2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <env.h>
  8. #include <init.h>
  9. #include <pci.h>
  10. #include <asm/processor.h>
  11. #include <asm/mmu.h>
  12. #include <asm/cache.h>
  13. #include <asm/immap_85xx.h>
  14. #include <asm/fsl_pci.h>
  15. #include <fsl_ddr_sdram.h>
  16. #include <asm/io.h>
  17. #include <asm/fsl_serdes.h>
  18. #include <miiphy.h>
  19. #include <linux/libfdt.h>
  20. #include <fdt_support.h>
  21. #include <tsec.h>
  22. #include <fsl_mdio.h>
  23. #include <netdev.h>
  24. #include "../common/sgmii_riser.h"
  25. int checkboard (void)
  26. {
  27. u8 vboot;
  28. u8 *pixis_base = (u8 *)PIXIS_BASE;
  29. printf("Board: MPC8572DS Sys ID: 0x%02x, "
  30. "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  31. in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
  32. in_8(pixis_base + PIXIS_PVER));
  33. vboot = in_8(pixis_base + PIXIS_VBOOT);
  34. switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) {
  35. case PIXIS_VBOOT_LBMAP_NOR0:
  36. puts ("vBank: 0\n");
  37. break;
  38. case PIXIS_VBOOT_LBMAP_PJET:
  39. puts ("Promjet\n");
  40. break;
  41. case PIXIS_VBOOT_LBMAP_NAND:
  42. puts ("NAND\n");
  43. break;
  44. case PIXIS_VBOOT_LBMAP_NOR1:
  45. puts ("vBank: 1\n");
  46. break;
  47. }
  48. return 0;
  49. }
  50. #if !defined(CONFIG_SPD_EEPROM)
  51. /*
  52. * Fixed sdram init -- doesn't use serial presence detect.
  53. */
  54. phys_size_t fixed_sdram (void)
  55. {
  56. volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  57. struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
  58. uint d_init;
  59. ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
  60. ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
  61. ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  62. ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  63. ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  64. ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  65. ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
  66. ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
  67. ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  68. ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
  69. ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
  70. ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
  71. #if defined (CONFIG_DDR_ECC)
  72. ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
  73. ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
  74. ddr->err_sbe = CONFIG_SYS_DDR_SBE;
  75. #endif
  76. asm("sync;isync");
  77. udelay(500);
  78. ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
  79. #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  80. d_init = 1;
  81. debug("DDR - 1st controller: memory initializing\n");
  82. /*
  83. * Poll until memory is initialized.
  84. * 512 Meg at 400 might hit this 200 times or so.
  85. */
  86. while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
  87. udelay(1000);
  88. }
  89. debug("DDR: memory initialized\n\n");
  90. asm("sync; isync");
  91. udelay(500);
  92. #endif
  93. return 512 * 1024 * 1024;
  94. }
  95. #endif
  96. #ifdef CONFIG_PCI
  97. void pci_init_board(void)
  98. {
  99. struct pci_controller *hose;
  100. fsl_pcie_init_board(0);
  101. hose = find_hose_by_cfg_addr((void *)(CONFIG_SYS_PCIE3_ADDR));
  102. if (hose) {
  103. u32 temp32;
  104. u8 uli_busno = hose->first_busno + 2;
  105. /*
  106. * Activate ULI1575 legacy chip by performing a fake
  107. * memory access. Needed to make ULI RTC work.
  108. * Device 1d has the first on-board memory BAR.
  109. */
  110. pci_hose_read_config_dword(hose, PCI_BDF(uli_busno, 0x1d, 0),
  111. PCI_BASE_ADDRESS_1, &temp32);
  112. if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
  113. void *p = pci_mem_to_virt(PCI_BDF(uli_busno, 0x1d, 0),
  114. temp32, 4, 0);
  115. debug(" uli1572 read to %p\n", p);
  116. in_be32(p);
  117. }
  118. }
  119. }
  120. #endif
  121. int board_early_init_r(void)
  122. {
  123. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  124. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  125. /*
  126. * Remap Boot flash + PROMJET region to caching-inhibited
  127. * so that flash can be erased properly.
  128. */
  129. /* Flush d-cache and invalidate i-cache of any FLASH data */
  130. flush_dcache();
  131. invalidate_icache();
  132. if (flash_esel == -1) {
  133. /* very unlikely unless something is messed up */
  134. puts("Error: Could not find TLB for FLASH BASE\n");
  135. flash_esel = 2; /* give our best effort to continue */
  136. } else {
  137. /* invalidate existing TLB entry for flash + promjet */
  138. disable_tlb(flash_esel);
  139. }
  140. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
  141. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
  142. 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
  143. return 0;
  144. }
  145. int board_eth_init(bd_t *bis)
  146. {
  147. #ifdef CONFIG_TSEC_ENET
  148. struct fsl_pq_mdio_info mdio_info;
  149. struct tsec_info_struct tsec_info[4];
  150. int num = 0;
  151. #ifdef CONFIG_TSEC1
  152. SET_STD_TSEC_INFO(tsec_info[num], 1);
  153. if (is_serdes_configured(SGMII_TSEC1)) {
  154. puts("eTSEC1 is in sgmii mode.\n");
  155. tsec_info[num].flags |= TSEC_SGMII;
  156. }
  157. num++;
  158. #endif
  159. #ifdef CONFIG_TSEC2
  160. SET_STD_TSEC_INFO(tsec_info[num], 2);
  161. if (is_serdes_configured(SGMII_TSEC2)) {
  162. puts("eTSEC2 is in sgmii mode.\n");
  163. tsec_info[num].flags |= TSEC_SGMII;
  164. }
  165. num++;
  166. #endif
  167. #ifdef CONFIG_TSEC3
  168. SET_STD_TSEC_INFO(tsec_info[num], 3);
  169. if (is_serdes_configured(SGMII_TSEC3)) {
  170. puts("eTSEC3 is in sgmii mode.\n");
  171. tsec_info[num].flags |= TSEC_SGMII;
  172. }
  173. num++;
  174. #endif
  175. #ifdef CONFIG_TSEC4
  176. SET_STD_TSEC_INFO(tsec_info[num], 4);
  177. if (is_serdes_configured(SGMII_TSEC4)) {
  178. puts("eTSEC4 is in sgmii mode.\n");
  179. tsec_info[num].flags |= TSEC_SGMII;
  180. }
  181. num++;
  182. #endif
  183. if (!num) {
  184. printf("No TSECs initialized\n");
  185. return 0;
  186. }
  187. #ifdef CONFIG_FSL_SGMII_RISER
  188. fsl_sgmii_riser_init(tsec_info, num);
  189. #endif
  190. mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
  191. mdio_info.name = DEFAULT_MII_NAME;
  192. fsl_pq_mdio_init(bis, &mdio_info);
  193. tsec_eth_init(bis, tsec_info, num);
  194. #endif
  195. return pci_eth_init(bis);
  196. }
  197. #if defined(CONFIG_OF_BOARD_SETUP)
  198. int ft_board_setup(void *blob, bd_t *bd)
  199. {
  200. phys_addr_t base;
  201. phys_size_t size;
  202. ft_cpu_setup(blob, bd);
  203. base = env_get_bootm_low();
  204. size = env_get_bootm_size();
  205. fdt_fixup_memory(blob, (u64)base, (u64)size);
  206. FT_FSL_PCI_SETUP;
  207. #ifdef CONFIG_FSL_SGMII_RISER
  208. fsl_sgmii_riser_fdt_fixup(blob);
  209. #endif
  210. return 0;
  211. }
  212. #endif