mpc8569mds.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2009-2010 Freescale Semiconductor.
  4. *
  5. * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  6. */
  7. #include <common.h>
  8. #include <console.h>
  9. #include <hwconfig.h>
  10. #include <init.h>
  11. #include <pci.h>
  12. #include <asm/processor.h>
  13. #include <asm/mmu.h>
  14. #include <asm/cache.h>
  15. #include <asm/immap_85xx.h>
  16. #include <asm/fsl_pci.h>
  17. #include <fsl_ddr_sdram.h>
  18. #include <asm/fsl_serdes.h>
  19. #include <asm/io.h>
  20. #include <spd_sdram.h>
  21. #include <i2c.h>
  22. #include <ioports.h>
  23. #include <linux/libfdt.h>
  24. #include <fdt_support.h>
  25. #include <fsl_esdhc.h>
  26. #include <phy.h>
  27. #include "bcsr.h"
  28. #if defined(CONFIG_PQ_MDS_PIB)
  29. #include "../common/pq-mds-pib.h"
  30. #endif
  31. const qe_iop_conf_t qe_iop_conf_tab[] = {
  32. /* QE_MUX_MDC */
  33. {2, 31, 1, 0, 1}, /* QE_MUX_MDC */
  34. /* QE_MUX_MDIO */
  35. {2, 30, 3, 0, 2}, /* QE_MUX_MDIO */
  36. #if defined(CONFIG_SYS_UCC_RGMII_MODE)
  37. /* UCC_1_RGMII */
  38. {2, 11, 2, 0, 1}, /* CLK12 */
  39. {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
  40. {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
  41. {0, 2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2 */
  42. {0, 3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
  43. {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
  44. {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
  45. {0, 8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
  46. {0, 9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
  47. {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
  48. {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
  49. {2, 8, 2, 0, 1}, /* ENET1_GRXCLK */
  50. {2, 20, 1, 0, 2}, /* ENET1_GTXCLK */
  51. /* UCC_2_RGMII */
  52. {2, 16, 2, 0, 3}, /* CLK17 */
  53. {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
  54. {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
  55. {0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2 */
  56. {0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3 */
  57. {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
  58. {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
  59. {0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2 */
  60. {0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3 */
  61. {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */
  62. {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */
  63. {2, 3, 2, 0, 1}, /* ENET2_GRXCLK */
  64. {2, 2, 1, 0, 2}, /* ENET2_GTXCLK */
  65. /* UCC_3_RGMII */
  66. {2, 11, 2, 0, 1}, /* CLK12 */
  67. {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
  68. {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
  69. {0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2 */
  70. {1, 0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3 */
  71. {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
  72. {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
  73. {1, 5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2 */
  74. {1, 6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3 */
  75. {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */
  76. {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */
  77. {2, 9, 2, 0, 2}, /* ENET3_GRXCLK */
  78. {2, 25, 1, 0, 2}, /* ENET3_GTXCLK */
  79. /* UCC_4_RGMII */
  80. {2, 16, 2, 0, 3}, /* CLK17 */
  81. {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
  82. {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
  83. {1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2 */
  84. {1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3 */
  85. {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
  86. {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
  87. {1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2 */
  88. {1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3 */
  89. {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */
  90. {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */
  91. {2, 17, 2, 0, 2}, /* ENET4_GRXCLK */
  92. {2, 24, 1, 0, 2}, /* ENET4_GTXCLK */
  93. #elif defined(CONFIG_SYS_UCC_RMII_MODE)
  94. /* UCC_1_RMII */
  95. {2, 15, 2, 0, 1}, /* CLK16 */
  96. {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
  97. {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
  98. {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
  99. {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
  100. {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
  101. {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
  102. /* UCC_2_RMII */
  103. {2, 15, 2, 0, 1}, /* CLK16 */
  104. {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
  105. {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
  106. {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
  107. {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
  108. {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */
  109. {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */
  110. /* UCC_3_RMII */
  111. {2, 15, 2, 0, 1}, /* CLK16 */
  112. {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
  113. {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
  114. {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
  115. {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
  116. {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */
  117. {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */
  118. /* UCC_4_RMII */
  119. {2, 15, 2, 0, 1}, /* CLK16 */
  120. {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
  121. {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
  122. {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
  123. {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
  124. {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */
  125. {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */
  126. #endif
  127. /* UART1 is muxed with QE PortF bit [9-12].*/
  128. {5, 12, 2, 0, 3}, /* UART1_SIN */
  129. {5, 9, 1, 0, 3}, /* UART1_SOUT */
  130. {5, 10, 2, 0, 3}, /* UART1_CTS_B */
  131. {5, 11, 1, 0, 2}, /* UART1_RTS_B */
  132. /* QE UART */
  133. {0, 19, 1, 0, 2}, /* QEUART_TX */
  134. {1, 17, 2, 0, 3}, /* QEUART_RX */
  135. {0, 25, 1, 0, 1}, /* QEUART_RTS */
  136. {1, 23, 2, 0, 1}, /* QEUART_CTS */
  137. /* QE USB */
  138. {5, 3, 1, 0, 1}, /* USB_OE */
  139. {5, 4, 1, 0, 2}, /* USB_TP */
  140. {5, 5, 1, 0, 2}, /* USB_TN */
  141. {5, 6, 2, 0, 2}, /* USB_RP */
  142. {5, 7, 2, 0, 1}, /* USB_RX */
  143. {5, 8, 2, 0, 1}, /* USB_RN */
  144. {2, 4, 2, 0, 2}, /* CLK5 */
  145. /* SPI Flash, M25P40 */
  146. {4, 27, 3, 0, 1}, /* SPI_MOSI */
  147. {4, 28, 3, 0, 1}, /* SPI_MISO */
  148. {4, 29, 3, 0, 1}, /* SPI_CLK */
  149. {4, 30, 1, 0, 0}, /* SPI_SEL, GPIO */
  150. {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
  151. };
  152. void local_bus_init(void);
  153. int board_early_init_f (void)
  154. {
  155. /*
  156. * Initialize local bus.
  157. */
  158. local_bus_init ();
  159. enable_8569mds_flash_write();
  160. #ifdef CONFIG_QE
  161. enable_8569mds_qe_uec();
  162. #endif
  163. #if CONFIG_SYS_I2C2_OFFSET
  164. /* Enable I2C2 signals instead of SD signals */
  165. volatile struct ccsr_gur *gur;
  166. gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000);
  167. gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK;
  168. gur->plppar1 |= PLPPAR1_I2C2_VAL;
  169. gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK;
  170. gur->plpdir1 |= PLPDIR1_I2C2_VAL;
  171. disable_8569mds_brd_eeprom_write_protect();
  172. #endif
  173. return 0;
  174. }
  175. int board_early_init_r(void)
  176. {
  177. const unsigned int flashbase = CONFIG_SYS_NAND_BASE;
  178. const u8 flash_esel = 0;
  179. /*
  180. * Remap Boot flash to caching-inhibited
  181. * so that flash can be erased properly.
  182. */
  183. /* Flush d-cache and invalidate i-cache of any FLASH data */
  184. flush_dcache();
  185. invalidate_icache();
  186. /* invalidate existing TLB entry for flash */
  187. disable_tlb(flash_esel);
  188. set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE, /* tlb, epn, rpn */
  189. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
  190. 0, flash_esel, /* ts, esel */
  191. BOOKE_PAGESZ_64M, 1); /* tsize, iprot */
  192. return 0;
  193. }
  194. int checkboard (void)
  195. {
  196. printf ("Board: 8569 MDS\n");
  197. return 0;
  198. }
  199. #if !defined(CONFIG_SPD_EEPROM)
  200. phys_size_t fixed_sdram(void)
  201. {
  202. struct ccsr_ddr __iomem *ddr =
  203. (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
  204. uint d_init;
  205. out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
  206. out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
  207. out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
  208. out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
  209. out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
  210. out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
  211. out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
  212. out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
  213. out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE);
  214. out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2);
  215. out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL);
  216. out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
  217. out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
  218. out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
  219. out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
  220. out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
  221. out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
  222. out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
  223. #if defined (CONFIG_DDR_ECC)
  224. out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN);
  225. out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS);
  226. out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE);
  227. #endif
  228. udelay(500);
  229. out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
  230. #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  231. d_init = 1;
  232. debug("DDR - 1st controller: memory initializing\n");
  233. /*
  234. * Poll until memory is initialized.
  235. * 512 Meg at 400 might hit this 200 times or so.
  236. */
  237. while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
  238. udelay(1000);
  239. }
  240. debug("DDR: memory initialized\n\n");
  241. udelay(500);
  242. #endif
  243. return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  244. }
  245. #endif
  246. /*
  247. * Initialize Local Bus
  248. */
  249. void
  250. local_bus_init(void)
  251. {
  252. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  253. volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  254. uint clkdiv;
  255. sys_info_t sysinfo;
  256. get_sys_info(&sysinfo);
  257. clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
  258. out_be32(&gur->lbiuiplldcr1, 0x00078080);
  259. if (clkdiv == 16)
  260. out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
  261. else if (clkdiv == 8)
  262. out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
  263. else if (clkdiv == 4)
  264. out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
  265. out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000);
  266. }
  267. static void fdt_board_disable_serial(void *blob, bd_t *bd, const char *alias)
  268. {
  269. const char *status = "disabled";
  270. int off;
  271. int err;
  272. off = fdt_path_offset(blob, alias);
  273. if (off < 0) {
  274. printf("WARNING: could not find %s alias: %s.\n", alias,
  275. fdt_strerror(off));
  276. return;
  277. }
  278. err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
  279. if (err) {
  280. printf("WARNING: could not set status for serial0: %s.\n",
  281. fdt_strerror(err));
  282. return;
  283. }
  284. }
  285. /*
  286. * Because of an erratum in prototype boards it is impossible to use eSDHC
  287. * without disabling UART0 (which makes it quite easy to 'brick' the board
  288. * by simply issung 'setenv hwconfig esdhc', and not able to interact with
  289. * U-Boot anylonger).
  290. *
  291. * So, but default we assume that the board is a prototype, which is a most
  292. * safe assumption. There is no way to determine board revision from a
  293. * register, so we use hwconfig.
  294. */
  295. static int prototype_board(void)
  296. {
  297. if (hwconfig_subarg("board", "rev", NULL))
  298. return hwconfig_subarg_cmp("board", "rev", "prototype");
  299. return 1;
  300. }
  301. static int esdhc_disables_uart0(void)
  302. {
  303. return prototype_board() ||
  304. hwconfig_subarg_cmp("esdhc", "mode", "4-bits");
  305. }
  306. static void fdt_board_fixup_qe_uart(void *blob, bd_t *bd)
  307. {
  308. u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
  309. const char *devtype = "serial";
  310. const char *compat = "ucc_uart";
  311. const char *clk = "brg9";
  312. u32 portnum = 0;
  313. int off = -1;
  314. if (!hwconfig("qe_uart"))
  315. return;
  316. if (hwconfig("esdhc") && esdhc_disables_uart0()) {
  317. printf("QE UART: won't enable with esdhc.\n");
  318. return;
  319. }
  320. fdt_board_disable_serial(blob, bd, "serial1");
  321. while (1) {
  322. const u32 *idx;
  323. int len;
  324. off = fdt_node_offset_by_compatible(blob, off, "ucc_geth");
  325. if (off < 0) {
  326. printf("WARNING: unable to fixup device tree for "
  327. "QE UART\n");
  328. return;
  329. }
  330. idx = fdt_getprop(blob, off, "cell-index", &len);
  331. if (!idx || len != sizeof(*idx) || *idx != fdt32_to_cpu(2))
  332. continue;
  333. break;
  334. }
  335. fdt_setprop(blob, off, "device_type", devtype, strlen(devtype) + 1);
  336. fdt_setprop(blob, off, "compatible", compat, strlen(compat) + 1);
  337. fdt_setprop(blob, off, "tx-clock-name", clk, strlen(clk) + 1);
  338. fdt_setprop(blob, off, "rx-clock-name", clk, strlen(clk) + 1);
  339. fdt_setprop(blob, off, "port-number", &portnum, sizeof(portnum));
  340. setbits_8(&bcsr[15], BCSR15_QEUART_EN);
  341. }
  342. #ifdef CONFIG_FSL_ESDHC
  343. int board_mmc_init(bd_t *bd)
  344. {
  345. struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  346. u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
  347. u8 bcsr6 = BCSR6_SD_CARD_1BIT;
  348. if (!hwconfig("esdhc"))
  349. return 0;
  350. printf("Enabling eSDHC...\n"
  351. " For eSDHC to function, I2C2 ");
  352. if (esdhc_disables_uart0()) {
  353. printf("and UART0 should be disabled.\n");
  354. printf(" Redirecting stderr, stdout and stdin to UART1...\n");
  355. console_assign(stderr, "eserial1");
  356. console_assign(stdout, "eserial1");
  357. console_assign(stdin, "eserial1");
  358. printf("Switched to UART1 (initial log has been printed to "
  359. "UART0).\n");
  360. clrsetbits_be32(&gur->plppar1, PLPPAR1_UART0_BIT_MASK,
  361. PLPPAR1_ESDHC_4BITS_VAL);
  362. clrsetbits_be32(&gur->plpdir1, PLPDIR1_UART0_BIT_MASK,
  363. PLPDIR1_ESDHC_4BITS_VAL);
  364. bcsr6 |= BCSR6_SD_CARD_4BITS;
  365. } else {
  366. printf("should be disabled.\n");
  367. }
  368. /* Assign I2C2 signals to eSDHC. */
  369. clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK,
  370. PLPPAR1_ESDHC_VAL);
  371. clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK,
  372. PLPDIR1_ESDHC_VAL);
  373. /* Mux I2C2 (and optionally UART0) signals to eSDHC. */
  374. setbits_8(&bcsr[6], bcsr6);
  375. return fsl_esdhc_mmc_init(bd);
  376. }
  377. static void fdt_board_fixup_esdhc(void *blob, bd_t *bd)
  378. {
  379. const char *status = "disabled";
  380. int off = -1;
  381. if (!hwconfig("esdhc"))
  382. return;
  383. if (esdhc_disables_uart0())
  384. fdt_board_disable_serial(blob, bd, "serial0");
  385. while (1) {
  386. const u32 *idx;
  387. int len;
  388. off = fdt_node_offset_by_compatible(blob, off, "fsl-i2c");
  389. if (off < 0)
  390. break;
  391. idx = fdt_getprop(blob, off, "cell-index", &len);
  392. if (!idx || len != sizeof(*idx))
  393. continue;
  394. if (*idx == 1) {
  395. fdt_setprop(blob, off, "status", status,
  396. strlen(status) + 1);
  397. break;
  398. }
  399. }
  400. if (hwconfig_subarg_cmp("esdhc", "mode", "4-bits")) {
  401. off = fdt_node_offset_by_compatible(blob, -1, "fsl,esdhc");
  402. if (off < 0) {
  403. printf("WARNING: could not find esdhc node\n");
  404. return;
  405. }
  406. fdt_delprop(blob, off, "sdhci,1-bit-only");
  407. }
  408. }
  409. #else
  410. static inline void fdt_board_fixup_esdhc(void *blob, bd_t *bd) {}
  411. #endif
  412. static void fdt_board_fixup_qe_usb(void *blob, bd_t *bd)
  413. {
  414. u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
  415. if (hwconfig_subarg_cmp("qe_usb", "speed", "low"))
  416. clrbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
  417. else
  418. setbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
  419. if (hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) {
  420. clrbits_8(&bcsr[17], BCSR17_USBVCC);
  421. clrbits_8(&bcsr[17], BCSR17_USBMODE);
  422. do_fixup_by_compat(blob, "fsl,mpc8569-qe-usb", "mode",
  423. "peripheral", sizeof("peripheral"), 1);
  424. } else {
  425. setbits_8(&bcsr[17], BCSR17_USBVCC);
  426. setbits_8(&bcsr[17], BCSR17_USBMODE);
  427. }
  428. clrbits_8(&bcsr[17], BCSR17_nUSBEN);
  429. }
  430. #ifdef CONFIG_PCI
  431. void pci_init_board(void)
  432. {
  433. #if defined(CONFIG_PQ_MDS_PIB)
  434. pib_init();
  435. #endif
  436. fsl_pcie_init_board(0);
  437. }
  438. #endif /* CONFIG_PCI */
  439. #if defined(CONFIG_OF_BOARD_SETUP)
  440. int ft_board_setup(void *blob, bd_t *bd)
  441. {
  442. #if defined(CONFIG_SYS_UCC_RMII_MODE)
  443. int nodeoff, off, err;
  444. unsigned int val;
  445. const u32 *ph;
  446. const u32 *index;
  447. /* fixup device tree for supporting rmii mode */
  448. nodeoff = -1;
  449. while ((nodeoff = fdt_node_offset_by_compatible(blob, nodeoff,
  450. "ucc_geth")) >= 0) {
  451. err = fdt_setprop_string(blob, nodeoff, "tx-clock-name",
  452. "clk16");
  453. if (err < 0) {
  454. printf("WARNING: could not set tx-clock-name %s.\n",
  455. fdt_strerror(err));
  456. break;
  457. }
  458. err = fdt_fixup_phy_connection(blob, nodeoff,
  459. PHY_INTERFACE_MODE_RMII);
  460. if (err < 0) {
  461. printf("WARNING: could not set phy-connection-type "
  462. "%s.\n", fdt_strerror(err));
  463. break;
  464. }
  465. index = fdt_getprop(blob, nodeoff, "cell-index", 0);
  466. if (index == NULL) {
  467. printf("WARNING: could not get cell-index of ucc\n");
  468. break;
  469. }
  470. ph = fdt_getprop(blob, nodeoff, "phy-handle", 0);
  471. if (ph == NULL) {
  472. printf("WARNING: could not get phy-handle of ucc\n");
  473. break;
  474. }
  475. off = fdt_node_offset_by_phandle(blob, *ph);
  476. if (off < 0) {
  477. printf("WARNING: could not get phy node %s.\n",
  478. fdt_strerror(err));
  479. break;
  480. }
  481. val = 0x7 + *index; /* RMII phy address starts from 0x8 */
  482. err = fdt_setprop(blob, off, "reg", &val, sizeof(u32));
  483. if (err < 0) {
  484. printf("WARNING: could not set reg for phy-handle "
  485. "%s.\n", fdt_strerror(err));
  486. break;
  487. }
  488. }
  489. #endif
  490. ft_cpu_setup(blob, bd);
  491. FT_FSL_PCI_SETUP;
  492. fdt_board_fixup_esdhc(blob, bd);
  493. fdt_board_fixup_qe_uart(blob, bd);
  494. fdt_board_fixup_qe_usb(blob, bd);
  495. return 0;
  496. }
  497. #endif