ls1021atwr.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <i2c.h>
  7. #include <init.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/immap_ls102xa.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/fsl_serdes.h>
  12. #include <asm/arch/ls102xa_devdis.h>
  13. #include <asm/arch/ls102xa_soc.h>
  14. #include <hwconfig.h>
  15. #include <mmc.h>
  16. #include <fsl_csu.h>
  17. #include <fsl_ifc.h>
  18. #include <fsl_immap.h>
  19. #include <netdev.h>
  20. #include <fsl_mdio.h>
  21. #include <tsec.h>
  22. #include <fsl_sec.h>
  23. #include <fsl_devdis.h>
  24. #include <spl.h>
  25. #include "../common/sleep.h"
  26. #ifdef CONFIG_U_QE
  27. #include <fsl_qe.h>
  28. #endif
  29. #include <fsl_validate.h>
  30. DECLARE_GLOBAL_DATA_PTR;
  31. #define VERSION_MASK 0x00FF
  32. #define BANK_MASK 0x0001
  33. #define CONFIG_RESET 0x1
  34. #define INIT_RESET 0x1
  35. #define CPLD_SET_MUX_SERDES 0x20
  36. #define CPLD_SET_BOOT_BANK 0x40
  37. #define BOOT_FROM_UPPER_BANK 0x0
  38. #define BOOT_FROM_LOWER_BANK 0x1
  39. #define LANEB_SATA (0x01)
  40. #define LANEB_SGMII1 (0x02)
  41. #define LANEC_SGMII1 (0x04)
  42. #define LANEC_PCIEX1 (0x08)
  43. #define LANED_PCIEX2 (0x10)
  44. #define LANED_SGMII2 (0x20)
  45. #define MASK_LANE_B 0x1
  46. #define MASK_LANE_C 0x2
  47. #define MASK_LANE_D 0x4
  48. #define MASK_SGMII 0x8
  49. #define KEEP_STATUS 0x0
  50. #define NEED_RESET 0x1
  51. #define SOFT_MUX_ON_I2C3_IFC 0x2
  52. #define SOFT_MUX_ON_CAN3_USB2 0x8
  53. #define SOFT_MUX_ON_QE_LCD 0x10
  54. #define PIN_I2C3_IFC_MUX_I2C3 0x0
  55. #define PIN_I2C3_IFC_MUX_IFC 0x1
  56. #define PIN_CAN3_USB2_MUX_USB2 0x0
  57. #define PIN_CAN3_USB2_MUX_CAN3 0x1
  58. #define PIN_QE_LCD_MUX_LCD 0x0
  59. #define PIN_QE_LCD_MUX_QE 0x1
  60. struct cpld_data {
  61. u8 cpld_ver; /* cpld revision */
  62. u8 cpld_ver_sub; /* cpld sub revision */
  63. u8 pcba_ver; /* pcb revision number */
  64. u8 system_rst; /* reset system by cpld */
  65. u8 soft_mux_on; /* CPLD override physical switches Enable */
  66. u8 cfg_rcw_src1; /* Reset config word 1 */
  67. u8 cfg_rcw_src2; /* Reset config word 2 */
  68. u8 vbank; /* Flash bank selection Control */
  69. u8 gpio; /* GPIO for TWR-ELEV */
  70. u8 i2c3_ifc_mux;
  71. u8 mux_spi2;
  72. u8 can3_usb2_mux; /* CAN3 and USB2 Selection */
  73. u8 qe_lcd_mux; /* QE and LCD Selection */
  74. u8 serdes_mux; /* Multiplexed pins for SerDes Lanes */
  75. u8 global_rst; /* reset with init CPLD reg to default */
  76. u8 rev1; /* Reserved */
  77. u8 rev2; /* Reserved */
  78. };
  79. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  80. static void cpld_show(void)
  81. {
  82. struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  83. printf("CPLD: V%x.%x\nPCBA: V%x.0\nVBank: %d\n",
  84. in_8(&cpld_data->cpld_ver) & VERSION_MASK,
  85. in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
  86. in_8(&cpld_data->pcba_ver) & VERSION_MASK,
  87. in_8(&cpld_data->vbank) & BANK_MASK);
  88. #ifdef CONFIG_DEBUG
  89. printf("soft_mux_on =%x\n",
  90. in_8(&cpld_data->soft_mux_on));
  91. printf("cfg_rcw_src1 =%x\n",
  92. in_8(&cpld_data->cfg_rcw_src1));
  93. printf("cfg_rcw_src2 =%x\n",
  94. in_8(&cpld_data->cfg_rcw_src2));
  95. printf("vbank =%x\n",
  96. in_8(&cpld_data->vbank));
  97. printf("gpio =%x\n",
  98. in_8(&cpld_data->gpio));
  99. printf("i2c3_ifc_mux =%x\n",
  100. in_8(&cpld_data->i2c3_ifc_mux));
  101. printf("mux_spi2 =%x\n",
  102. in_8(&cpld_data->mux_spi2));
  103. printf("can3_usb2_mux =%x\n",
  104. in_8(&cpld_data->can3_usb2_mux));
  105. printf("qe_lcd_mux =%x\n",
  106. in_8(&cpld_data->qe_lcd_mux));
  107. printf("serdes_mux =%x\n",
  108. in_8(&cpld_data->serdes_mux));
  109. #endif
  110. }
  111. #endif
  112. int checkboard(void)
  113. {
  114. puts("Board: LS1021ATWR\n");
  115. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  116. cpld_show();
  117. #endif
  118. return 0;
  119. }
  120. void ddrmc_init(void)
  121. {
  122. struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
  123. u32 temp_sdram_cfg, tmp;
  124. out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
  125. out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
  126. out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
  127. out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
  128. out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
  129. out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
  130. out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
  131. out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
  132. out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
  133. #ifdef CONFIG_DEEP_SLEEP
  134. if (is_warm_boot()) {
  135. out_be32(&ddr->sdram_cfg_2,
  136. DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
  137. out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
  138. out_be32(&ddr->init_ext_addr, (1 << 31));
  139. /* DRAM VRef will not be trained */
  140. out_be32(&ddr->ddr_cdr2,
  141. DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
  142. } else
  143. #endif
  144. {
  145. out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
  146. out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
  147. }
  148. out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
  149. out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
  150. out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
  151. out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
  152. out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
  153. out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
  154. out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
  155. out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
  156. out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
  157. out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
  158. /* DDR erratum A-009942 */
  159. tmp = in_be32(&ddr->debug[28]);
  160. out_be32(&ddr->debug[28], tmp | 0x0070006f);
  161. udelay(1);
  162. #ifdef CONFIG_DEEP_SLEEP
  163. if (is_warm_boot()) {
  164. /* enter self-refresh */
  165. temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
  166. temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
  167. out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
  168. temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
  169. } else
  170. #endif
  171. temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
  172. out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
  173. #ifdef CONFIG_DEEP_SLEEP
  174. if (is_warm_boot()) {
  175. /* exit self-refresh */
  176. temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
  177. temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
  178. out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
  179. }
  180. #endif
  181. }
  182. int dram_init(void)
  183. {
  184. #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
  185. ddrmc_init();
  186. #endif
  187. erratum_a008850_post();
  188. gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  189. #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
  190. fsl_dp_resume();
  191. #endif
  192. return 0;
  193. }
  194. int board_eth_init(bd_t *bis)
  195. {
  196. return pci_eth_init(bis);
  197. }
  198. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  199. static void convert_serdes_mux(int type, int need_reset)
  200. {
  201. char current_serdes;
  202. struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  203. current_serdes = cpld_data->serdes_mux;
  204. switch (type) {
  205. case LANEB_SATA:
  206. current_serdes &= ~MASK_LANE_B;
  207. break;
  208. case LANEB_SGMII1:
  209. current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
  210. break;
  211. case LANEC_SGMII1:
  212. current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
  213. break;
  214. case LANED_SGMII2:
  215. current_serdes |= MASK_LANE_D;
  216. break;
  217. case LANEC_PCIEX1:
  218. current_serdes |= MASK_LANE_C;
  219. break;
  220. case (LANED_PCIEX2 | LANEC_PCIEX1):
  221. current_serdes |= MASK_LANE_C;
  222. current_serdes &= ~MASK_LANE_D;
  223. break;
  224. default:
  225. printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
  226. return;
  227. }
  228. cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
  229. cpld_data->serdes_mux = current_serdes;
  230. if (need_reset == 1) {
  231. printf("Reset board to enable configuration\n");
  232. cpld_data->system_rst = CONFIG_RESET;
  233. }
  234. }
  235. int config_serdes_mux(void)
  236. {
  237. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  238. u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
  239. protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
  240. switch (protocol) {
  241. case 0x10:
  242. convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
  243. convert_serdes_mux(LANED_PCIEX2 |
  244. LANEC_PCIEX1, KEEP_STATUS);
  245. break;
  246. case 0x20:
  247. convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
  248. convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
  249. convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
  250. break;
  251. case 0x30:
  252. convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
  253. convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
  254. convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
  255. break;
  256. case 0x70:
  257. convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
  258. convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
  259. convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
  260. break;
  261. }
  262. return 0;
  263. }
  264. #endif
  265. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  266. int config_board_mux(void)
  267. {
  268. struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  269. int conflict_flag;
  270. conflict_flag = 0;
  271. if (hwconfig("i2c3")) {
  272. conflict_flag++;
  273. cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
  274. cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3;
  275. }
  276. if (hwconfig("ifc")) {
  277. conflict_flag++;
  278. /* some signals can not enable simultaneous*/
  279. if (conflict_flag > 1)
  280. goto conflict;
  281. cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
  282. cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC;
  283. }
  284. conflict_flag = 0;
  285. if (hwconfig("usb2")) {
  286. conflict_flag++;
  287. cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
  288. cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2;
  289. }
  290. if (hwconfig("can3")) {
  291. conflict_flag++;
  292. /* some signals can not enable simultaneous*/
  293. if (conflict_flag > 1)
  294. goto conflict;
  295. cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
  296. cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3;
  297. }
  298. conflict_flag = 0;
  299. if (hwconfig("lcd")) {
  300. conflict_flag++;
  301. cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
  302. cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD;
  303. }
  304. if (hwconfig("qe")) {
  305. conflict_flag++;
  306. /* some signals can not enable simultaneous*/
  307. if (conflict_flag > 1)
  308. goto conflict;
  309. cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
  310. cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE;
  311. }
  312. return 0;
  313. conflict:
  314. printf("WARNING: pin conflict! MUX setting may failed!\n");
  315. return 0;
  316. }
  317. #endif
  318. int board_early_init_f(void)
  319. {
  320. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  321. #ifdef CONFIG_TSEC_ENET
  322. /* clear BD & FR bits for BE BD's and frame data */
  323. clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
  324. out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
  325. #endif
  326. #ifdef CONFIG_FSL_IFC
  327. init_early_memctl_regs();
  328. #endif
  329. arch_soc_init();
  330. #if defined(CONFIG_DEEP_SLEEP)
  331. if (is_warm_boot()) {
  332. timer_init();
  333. dram_init();
  334. }
  335. #endif
  336. return 0;
  337. }
  338. #ifdef CONFIG_SPL_BUILD
  339. void board_init_f(ulong dummy)
  340. {
  341. void (*second_uboot)(void);
  342. /* Clear the BSS */
  343. memset(__bss_start, 0, __bss_end - __bss_start);
  344. get_clocks();
  345. #if defined(CONFIG_DEEP_SLEEP)
  346. if (is_warm_boot())
  347. fsl_dp_disable_console();
  348. #endif
  349. preloader_console_init();
  350. timer_init();
  351. dram_init();
  352. /* Allow OCRAM access permission as R/W */
  353. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  354. enable_layerscape_ns_access();
  355. #endif
  356. /*
  357. * if it is woken up from deep sleep, then jump to second
  358. * stage uboot and continue executing without recopying
  359. * it from SD since it has already been reserved in memeory
  360. * in last boot.
  361. */
  362. if (is_warm_boot()) {
  363. second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
  364. second_uboot();
  365. }
  366. board_init_r(NULL, 0);
  367. }
  368. #endif
  369. #ifdef CONFIG_DEEP_SLEEP
  370. /* program the regulator (MC34VR500) to support deep sleep */
  371. void ls1twr_program_regulator(void)
  372. {
  373. unsigned int i2c_bus;
  374. u8 i2c_device_id;
  375. #define LS1TWR_I2C_BUS_MC34VR500 1
  376. #define MC34VR500_ADDR 0x8
  377. #define MC34VR500_DEVICEID 0x4
  378. #define MC34VR500_DEVICEID_MASK 0x0f
  379. i2c_bus = i2c_get_bus_num();
  380. i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500);
  381. i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) &
  382. MC34VR500_DEVICEID_MASK;
  383. if (i2c_device_id != MC34VR500_DEVICEID) {
  384. printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
  385. return;
  386. }
  387. i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4);
  388. i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4);
  389. i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38);
  390. i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37);
  391. i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30);
  392. i2c_set_bus_num(i2c_bus);
  393. }
  394. #endif
  395. int board_init(void)
  396. {
  397. #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  398. erratum_a010315();
  399. #endif
  400. #ifndef CONFIG_SYS_FSL_NO_SERDES
  401. fsl_serdes_init();
  402. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  403. config_serdes_mux();
  404. #endif
  405. #endif
  406. ls102xa_smmu_stream_id_init();
  407. #ifdef CONFIG_U_QE
  408. u_qe_init();
  409. #endif
  410. #ifdef CONFIG_DEEP_SLEEP
  411. ls1twr_program_regulator();
  412. #endif
  413. return 0;
  414. }
  415. #if defined(CONFIG_SPL_BUILD)
  416. void spl_board_init(void)
  417. {
  418. ls102xa_smmu_stream_id_init();
  419. }
  420. #endif
  421. #ifdef CONFIG_BOARD_LATE_INIT
  422. int board_late_init(void)
  423. {
  424. #ifdef CONFIG_CHAIN_OF_TRUST
  425. fsl_setenv_chain_of_trust();
  426. #endif
  427. return 0;
  428. }
  429. #endif
  430. #if defined(CONFIG_MISC_INIT_R)
  431. int misc_init_r(void)
  432. {
  433. #ifdef CONFIG_FSL_DEVICE_DISABLE
  434. device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
  435. #endif
  436. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  437. config_board_mux();
  438. #endif
  439. #ifdef CONFIG_FSL_CAAM
  440. return sec_init();
  441. #endif
  442. }
  443. #endif
  444. #if defined(CONFIG_DEEP_SLEEP)
  445. void board_sleep_prepare(void)
  446. {
  447. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  448. enable_layerscape_ns_access();
  449. #endif
  450. }
  451. #endif
  452. int ft_board_setup(void *blob, bd_t *bd)
  453. {
  454. ft_cpu_setup(blob, bd);
  455. #ifdef CONFIG_PCI
  456. ft_pci_setup(blob, bd);
  457. #endif
  458. return 0;
  459. }
  460. u8 flash_read8(void *addr)
  461. {
  462. return __raw_readb(addr + 1);
  463. }
  464. void flash_write16(u16 val, void *addr)
  465. {
  466. u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
  467. __raw_writew(shftval, addr);
  468. }
  469. u16 flash_read16(void *addr)
  470. {
  471. u16 val = __raw_readw(addr);
  472. return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
  473. }
  474. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) \
  475. && !defined(CONFIG_SPL_BUILD)
  476. static void convert_flash_bank(char bank)
  477. {
  478. struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  479. printf("Now switch to boot from flash bank %d.\n", bank);
  480. cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
  481. cpld_data->vbank = bank;
  482. printf("Reset board to enable configuration.\n");
  483. cpld_data->system_rst = CONFIG_RESET;
  484. }
  485. static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
  486. char * const argv[])
  487. {
  488. if (argc != 2)
  489. return CMD_RET_USAGE;
  490. if (strcmp(argv[1], "0") == 0)
  491. convert_flash_bank(BOOT_FROM_UPPER_BANK);
  492. else if (strcmp(argv[1], "1") == 0)
  493. convert_flash_bank(BOOT_FROM_LOWER_BANK);
  494. else
  495. return CMD_RET_USAGE;
  496. return 0;
  497. }
  498. U_BOOT_CMD(
  499. boot_bank, 2, 0, flash_bank_cmd,
  500. "Flash bank Selection Control",
  501. "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
  502. );
  503. static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
  504. char * const argv[])
  505. {
  506. struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  507. if (argc > 2)
  508. return CMD_RET_USAGE;
  509. if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
  510. cpld_data->system_rst = CONFIG_RESET;
  511. else if (strcmp(argv[1], "init") == 0)
  512. cpld_data->global_rst = INIT_RESET;
  513. else
  514. return CMD_RET_USAGE;
  515. return 0;
  516. }
  517. U_BOOT_CMD(
  518. cpld_reset, 2, 0, cpld_reset_cmd,
  519. "Reset via CPLD",
  520. "conf\n"
  521. " -reset with current CPLD configuration\n"
  522. "init\n"
  523. " -reset and initial CPLD configuration with default value"
  524. );
  525. static void print_serdes_mux(void)
  526. {
  527. char current_serdes;
  528. struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  529. current_serdes = cpld_data->serdes_mux;
  530. printf("Serdes Lane B: ");
  531. if ((current_serdes & MASK_LANE_B) == 0)
  532. printf("SATA,\n");
  533. else
  534. printf("SGMII 1,\n");
  535. printf("Serdes Lane C: ");
  536. if ((current_serdes & MASK_LANE_C) == 0)
  537. printf("SGMII 1,\n");
  538. else
  539. printf("PCIe,\n");
  540. printf("Serdes Lane D: ");
  541. if ((current_serdes & MASK_LANE_D) == 0)
  542. printf("PCIe,\n");
  543. else
  544. printf("SGMII 2,\n");
  545. printf("SGMII 1 is on lane ");
  546. if ((current_serdes & MASK_SGMII) == 0)
  547. printf("C.\n");
  548. else
  549. printf("B.\n");
  550. }
  551. static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
  552. char * const argv[])
  553. {
  554. if (argc != 2)
  555. return CMD_RET_USAGE;
  556. if (strcmp(argv[1], "sata") == 0) {
  557. printf("Set serdes lane B to SATA.\n");
  558. convert_serdes_mux(LANEB_SATA, NEED_RESET);
  559. } else if (strcmp(argv[1], "sgmii1b") == 0) {
  560. printf("Set serdes lane B to SGMII 1.\n");
  561. convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
  562. } else if (strcmp(argv[1], "sgmii1c") == 0) {
  563. printf("Set serdes lane C to SGMII 1.\n");
  564. convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
  565. } else if (strcmp(argv[1], "sgmii2") == 0) {
  566. printf("Set serdes lane D to SGMII 2.\n");
  567. convert_serdes_mux(LANED_SGMII2, NEED_RESET);
  568. } else if (strcmp(argv[1], "pciex1") == 0) {
  569. printf("Set serdes lane C to PCIe X1.\n");
  570. convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
  571. } else if (strcmp(argv[1], "pciex2") == 0) {
  572. printf("Set serdes lane C & lane D to PCIe X2.\n");
  573. convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
  574. } else if (strcmp(argv[1], "show") == 0) {
  575. print_serdes_mux();
  576. } else {
  577. return CMD_RET_USAGE;
  578. }
  579. return 0;
  580. }
  581. U_BOOT_CMD(
  582. lane_bank, 2, 0, serdes_mux_cmd,
  583. "Multiplexed function setting for SerDes Lanes",
  584. "sata\n"
  585. " -change lane B to sata\n"
  586. "lane_bank sgmii1b\n"
  587. " -change lane B to SGMII1\n"
  588. "lane_bank sgmii1c\n"
  589. " -change lane C to SGMII1\n"
  590. "lane_bank sgmii2\n"
  591. " -change lane D to SGMII2\n"
  592. "lane_bank pciex1\n"
  593. " -change lane C to PCIeX1\n"
  594. "lane_bank pciex2\n"
  595. " -change lane C & lane D to PCIeX2\n"
  596. "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
  597. );
  598. #endif