ls1021atsn.c 5.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261
  1. // SPDX-License-Identifier: GPL-2.0
  2. /* Copyright 2016-2019 NXP Semiconductors
  3. */
  4. #include <common.h>
  5. #include <init.h>
  6. #include <asm/arch-ls102xa/ls102xa_soc.h>
  7. #include <asm/arch/ls102xa_devdis.h>
  8. #include <asm/arch/immap_ls102xa.h>
  9. #include <asm/arch/ls102xa_soc.h>
  10. #include <asm/arch/fsl_serdes.h>
  11. #include "../common/sleep.h"
  12. #include <fsl_validate.h>
  13. #include <fsl_immap.h>
  14. #include <fsl_csu.h>
  15. #include <netdev.h>
  16. #include <spl.h>
  17. #ifdef CONFIG_U_QE
  18. #include <fsl_qe.h>
  19. #endif
  20. DECLARE_GLOBAL_DATA_PTR;
  21. static void ddrmc_init(void)
  22. {
  23. #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
  24. struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
  25. u32 temp_sdram_cfg, tmp;
  26. out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
  27. out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
  28. out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
  29. out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
  30. out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
  31. out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
  32. out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
  33. out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
  34. out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
  35. #ifdef CONFIG_DEEP_SLEEP
  36. if (is_warm_boot()) {
  37. out_be32(&ddr->sdram_cfg_2,
  38. DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
  39. out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
  40. out_be32(&ddr->init_ext_addr, (1 << 31));
  41. /* DRAM VRef will not be trained */
  42. out_be32(&ddr->ddr_cdr2,
  43. DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
  44. } else
  45. #endif
  46. {
  47. out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
  48. out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
  49. }
  50. out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
  51. out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
  52. out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
  53. out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
  54. out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
  55. out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
  56. out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
  57. out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
  58. out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
  59. out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
  60. /* DDR erratum A-009942 */
  61. tmp = in_be32(&ddr->debug[28]);
  62. out_be32(&ddr->debug[28], tmp | 0x0070006f);
  63. udelay(1);
  64. #ifdef CONFIG_DEEP_SLEEP
  65. if (is_warm_boot()) {
  66. /* enter self-refresh */
  67. temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
  68. temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
  69. out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
  70. temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
  71. } else
  72. #endif
  73. temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
  74. out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
  75. #ifdef CONFIG_DEEP_SLEEP
  76. if (is_warm_boot()) {
  77. /* exit self-refresh */
  78. temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
  79. temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
  80. out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
  81. }
  82. #endif
  83. #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
  84. }
  85. int dram_init(void)
  86. {
  87. ddrmc_init();
  88. erratum_a008850_post();
  89. gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  90. #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
  91. fsl_dp_resume();
  92. #endif
  93. return 0;
  94. }
  95. int board_eth_init(bd_t *bis)
  96. {
  97. return pci_eth_init(bis);
  98. }
  99. int board_early_init_f(void)
  100. {
  101. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  102. #ifdef CONFIG_TSEC_ENET
  103. /*
  104. * Clear BD & FR bits for big endian BD's and frame data (aka set
  105. * correct eTSEC endianness). This is crucial in ensuring that it does
  106. * not report Data Parity Errors in its RX/TX FIFOs when attempting to
  107. * send traffic.
  108. */
  109. clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
  110. /* EC3_GTX_CLK125 (of enet2) used for all RGMII interfaces */
  111. out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
  112. #endif
  113. arch_soc_init();
  114. #if defined(CONFIG_DEEP_SLEEP)
  115. if (is_warm_boot()) {
  116. timer_init();
  117. dram_init();
  118. }
  119. #endif
  120. return 0;
  121. }
  122. #ifdef CONFIG_SPL_BUILD
  123. void board_init_f(ulong dummy)
  124. {
  125. void (*second_uboot)(void);
  126. /* Clear the BSS */
  127. memset(__bss_start, 0, __bss_end - __bss_start);
  128. get_clocks();
  129. #if defined(CONFIG_DEEP_SLEEP)
  130. if (is_warm_boot())
  131. fsl_dp_disable_console();
  132. #endif
  133. preloader_console_init();
  134. dram_init();
  135. /* Allow OCRAM access permission as R/W */
  136. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  137. enable_layerscape_ns_access();
  138. enable_layerscape_ns_access();
  139. #endif
  140. /*
  141. * if it is woken up from deep sleep, then jump to second
  142. * stage U-Boot and continue executing without recopying
  143. * it from SD since it has already been reserved in memory
  144. * in last boot.
  145. */
  146. if (is_warm_boot()) {
  147. second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
  148. second_uboot();
  149. }
  150. board_init_r(NULL, 0);
  151. }
  152. #endif
  153. int board_init(void)
  154. {
  155. #ifndef CONFIG_SYS_FSL_NO_SERDES
  156. fsl_serdes_init();
  157. #endif
  158. ls102xa_smmu_stream_id_init();
  159. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  160. enable_layerscape_ns_access();
  161. #endif
  162. #ifdef CONFIG_U_QE
  163. u_qe_init();
  164. #endif
  165. return 0;
  166. }
  167. #if defined(CONFIG_SPL_BUILD)
  168. void spl_board_init(void)
  169. {
  170. ls102xa_smmu_stream_id_init();
  171. }
  172. #endif
  173. #ifdef CONFIG_BOARD_LATE_INIT
  174. int board_late_init(void)
  175. {
  176. #ifdef CONFIG_CHAIN_OF_TRUST
  177. fsl_setenv_chain_of_trust();
  178. #endif
  179. return 0;
  180. }
  181. #endif
  182. #if defined(CONFIG_MISC_INIT_R)
  183. int misc_init_r(void)
  184. {
  185. #ifdef CONFIG_FSL_DEVICE_DISABLE
  186. device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
  187. #endif
  188. #ifdef CONFIG_FSL_CAAM
  189. return sec_init();
  190. #endif
  191. }
  192. #endif
  193. #if defined(CONFIG_DEEP_SLEEP)
  194. void board_sleep_prepare(void)
  195. {
  196. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  197. enable_layerscape_ns_access();
  198. #endif
  199. }
  200. #endif
  201. int ft_board_setup(void *blob, bd_t *bd)
  202. {
  203. ft_cpu_setup(blob, bd);
  204. #ifdef CONFIG_PCI
  205. ft_pci_setup(blob, bd);
  206. #endif
  207. return 0;
  208. }