ls1021aiot.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <init.h>
  7. #include <asm/arch/immap_ls102xa.h>
  8. #include <asm/arch/clock.h>
  9. #include <asm/arch/fsl_serdes.h>
  10. #include <asm/arch/ls102xa_stream_id.h>
  11. #include <asm/arch/ls102xa_devdis.h>
  12. #include <asm/arch/ls102xa_soc.h>
  13. #include <fsl_csu.h>
  14. #include <fsl_immap.h>
  15. #include <netdev.h>
  16. #include <fsl_mdio.h>
  17. #include <tsec.h>
  18. #include <spl.h>
  19. #include <fsl_validate.h>
  20. #include "../common/sleep.h"
  21. DECLARE_GLOBAL_DATA_PTR;
  22. #define DDR_SIZE 0x40000000
  23. int checkboard(void)
  24. {
  25. puts("Board: LS1021AIOT\n");
  26. #ifndef CONFIG_QSPI_BOOT
  27. struct ccsr_gur *dcfg = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
  28. u32 cpldrev;
  29. cpldrev = in_be32(&dcfg->gpporcr1);
  30. printf("CPLD: V%d.%d\n", ((cpldrev >> 28) & 0xf), ((cpldrev >> 24) &
  31. 0xf));
  32. #endif
  33. return 0;
  34. }
  35. void ddrmc_init(void)
  36. {
  37. struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
  38. u32 temp_sdram_cfg, tmp;
  39. out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
  40. out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
  41. out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
  42. out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
  43. out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
  44. out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
  45. out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
  46. out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
  47. out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
  48. out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
  49. out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
  50. out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
  51. out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
  52. out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
  53. out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
  54. out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
  55. out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
  56. out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
  57. out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
  58. out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
  59. out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
  60. /* DDR erratum A-009942 */
  61. tmp = in_be32(&ddr->debug[28]);
  62. out_be32(&ddr->debug[28], tmp | 0x0070006f);
  63. udelay(500);
  64. temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
  65. out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
  66. }
  67. int dram_init(void)
  68. {
  69. #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
  70. ddrmc_init();
  71. #endif
  72. erratum_a008850_post();
  73. gd->ram_size = DDR_SIZE;
  74. return 0;
  75. }
  76. #ifdef CONFIG_TSEC_ENET
  77. int board_eth_init(bd_t *bis)
  78. {
  79. struct fsl_pq_mdio_info mdio_info;
  80. struct tsec_info_struct tsec_info[4];
  81. int num = 0;
  82. #ifdef CONFIG_TSEC1
  83. SET_STD_TSEC_INFO(tsec_info[num], 1);
  84. if (is_serdes_configured(SGMII_TSEC1)) {
  85. puts("eTSEC1 is in sgmii mode.\n");
  86. tsec_info[num].flags |= TSEC_SGMII;
  87. }
  88. num++;
  89. #endif
  90. #ifdef CONFIG_TSEC2
  91. SET_STD_TSEC_INFO(tsec_info[num], 2);
  92. if (is_serdes_configured(SGMII_TSEC2)) {
  93. puts("eTSEC2 is in sgmii mode.\n");
  94. tsec_info[num].flags |= TSEC_SGMII;
  95. }
  96. num++;
  97. #endif
  98. if (!num) {
  99. printf("No TSECs initialized\n");
  100. return 0;
  101. }
  102. mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
  103. mdio_info.name = DEFAULT_MII_NAME;
  104. fsl_pq_mdio_init(bis, &mdio_info);
  105. tsec_eth_init(bis, tsec_info, num);
  106. return pci_eth_init(bis);
  107. }
  108. #endif
  109. int board_early_init_f(void)
  110. {
  111. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  112. #ifdef CONFIG_TSEC_ENET
  113. /* clear BD & FR bits for BE BD's and frame data */
  114. clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
  115. out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
  116. #endif
  117. arch_soc_init();
  118. return 0;
  119. }
  120. #ifdef CONFIG_SPL_BUILD
  121. void board_init_f(ulong dummy)
  122. {
  123. /* Clear the BSS */
  124. memset(__bss_start, 0, __bss_end - __bss_start);
  125. get_clocks();
  126. preloader_console_init();
  127. dram_init();
  128. /* Allow OCRAM access permission as R/W */
  129. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  130. enable_layerscape_ns_access();
  131. #endif
  132. board_init_r(NULL, 0);
  133. }
  134. #endif
  135. int board_init(void)
  136. {
  137. #ifndef CONFIG_SYS_FSL_NO_SERDES
  138. fsl_serdes_init();
  139. #endif
  140. ls102xa_smmu_stream_id_init();
  141. return 0;
  142. }
  143. #ifdef CONFIG_BOARD_LATE_INIT
  144. int board_late_init(void)
  145. {
  146. return 0;
  147. }
  148. #endif
  149. #if defined(CONFIG_MISC_INIT_R)
  150. int misc_init_r(void)
  151. {
  152. #ifdef CONFIG_FSL_DEVICE_DISABLE
  153. device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
  154. #endif
  155. #ifdef CONFIG_FSL_CAAM
  156. return sec_init();
  157. #endif
  158. }
  159. #endif
  160. int ft_board_setup(void *blob, bd_t *bd)
  161. {
  162. ft_cpu_setup(blob, bd);
  163. #ifdef CONFIG_PCI
  164. ft_pci_setup(blob, bd);
  165. #endif
  166. return 0;
  167. }
  168. void flash_write16(u16 val, void *addr)
  169. {
  170. u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
  171. __raw_writew(shftval, addr);
  172. }
  173. u16 flash_read16(void *addr)
  174. {
  175. u16 val = __raw_readw(addr);
  176. return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
  177. }