imx8mq_evk.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2018 NXP
  4. */
  5. #include <common.h>
  6. #include <env.h>
  7. #include <init.h>
  8. #include <malloc.h>
  9. #include <errno.h>
  10. #include <asm/io.h>
  11. #include <miiphy.h>
  12. #include <netdev.h>
  13. #include <asm/mach-imx/iomux-v3.h>
  14. #include <asm-generic/gpio.h>
  15. #include <fsl_esdhc_imx.h>
  16. #include <mmc.h>
  17. #include <asm/arch/imx8mq_pins.h>
  18. #include <asm/arch/sys_proto.h>
  19. #include <asm/mach-imx/gpio.h>
  20. #include <asm/mach-imx/mxc_i2c.h>
  21. #include <asm/arch/clock.h>
  22. #include <spl.h>
  23. #include <power/pmic.h>
  24. #include <power/pfuze100_pmic.h>
  25. #include "../common/pfuze.h"
  26. DECLARE_GLOBAL_DATA_PTR;
  27. #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
  28. #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
  29. static iomux_v3_cfg_t const wdog_pads[] = {
  30. IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  31. };
  32. static iomux_v3_cfg_t const uart_pads[] = {
  33. IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  34. IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  35. };
  36. int board_early_init_f(void)
  37. {
  38. struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  39. imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  40. set_wdog_reset(wdog);
  41. imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  42. return 0;
  43. }
  44. int dram_init(void)
  45. {
  46. /* rom_pointer[1] contains the size of TEE occupies */
  47. if (rom_pointer[1])
  48. gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
  49. else
  50. gd->ram_size = PHYS_SDRAM_SIZE;
  51. return 0;
  52. }
  53. #ifdef CONFIG_FEC_MXC
  54. #define FEC_RST_PAD IMX_GPIO_NR(1, 9)
  55. static iomux_v3_cfg_t const fec1_rst_pads[] = {
  56. IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
  57. };
  58. static void setup_iomux_fec(void)
  59. {
  60. imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
  61. ARRAY_SIZE(fec1_rst_pads));
  62. gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
  63. gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
  64. udelay(500);
  65. gpio_direction_output(IMX_GPIO_NR(1, 9), 1);
  66. }
  67. static int setup_fec(void)
  68. {
  69. struct iomuxc_gpr_base_regs *gpr =
  70. (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  71. setup_iomux_fec();
  72. /* Use 125M anatop REF_CLK1 for ENET1, not from external */
  73. clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
  74. return set_clk_enet(ENET_125MHZ);
  75. }
  76. int board_phy_config(struct phy_device *phydev)
  77. {
  78. /* enable rgmii rxc skew and phy mode select to RGMII copper */
  79. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
  80. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
  81. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
  82. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
  83. if (phydev->drv->config)
  84. phydev->drv->config(phydev);
  85. return 0;
  86. }
  87. #endif
  88. int board_init(void)
  89. {
  90. #ifdef CONFIG_FEC_MXC
  91. setup_fec();
  92. #endif
  93. return 0;
  94. }
  95. int board_mmc_get_env_dev(int devno)
  96. {
  97. return devno;
  98. }
  99. int board_late_init(void)
  100. {
  101. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  102. env_set("board_name", "EVK");
  103. env_set("board_rev", "iMX8MQ");
  104. #endif
  105. return 0;
  106. }