dh_imx6.c 5.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * DHCOM DH-iMX6 PDK board support
  4. *
  5. * Copyright (C) 2017 Marek Vasut <marex@denx.de>
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <init.h>
  10. #include <dm/device-internal.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/crm_regs.h>
  13. #include <asm/arch/imx-regs.h>
  14. #include <asm/arch/iomux.h>
  15. #include <asm/arch/mx6-pins.h>
  16. #include <asm/arch/sys_proto.h>
  17. #include <asm/gpio.h>
  18. #include <asm/io.h>
  19. #include <asm/mach-imx/boot_mode.h>
  20. #include <asm/mach-imx/iomux-v3.h>
  21. #include <asm/mach-imx/sata.h>
  22. #include <ahci.h>
  23. #include <dwc_ahsata.h>
  24. #include <env.h>
  25. #include <errno.h>
  26. #include <fsl_esdhc_imx.h>
  27. #include <fuse.h>
  28. #include <i2c_eeprom.h>
  29. #include <miiphy.h>
  30. #include <mmc.h>
  31. #include <net.h>
  32. #include <netdev.h>
  33. #include <usb.h>
  34. #include <usb/ehci-ci.h>
  35. DECLARE_GLOBAL_DATA_PTR;
  36. int dram_init(void)
  37. {
  38. gd->ram_size = imx_ddr_size();
  39. return 0;
  40. }
  41. /*
  42. * Do not overwrite the console
  43. * Use always serial for U-Boot console
  44. */
  45. int overwrite_console(void)
  46. {
  47. return 1;
  48. }
  49. #ifdef CONFIG_FEC_MXC
  50. static void eth_phy_reset(void)
  51. {
  52. /* Reset PHY */
  53. gpio_direction_output(IMX_GPIO_NR(5, 0) , 0);
  54. udelay(500);
  55. gpio_set_value(IMX_GPIO_NR(5, 0), 1);
  56. /* Enable VIO */
  57. gpio_direction_output(IMX_GPIO_NR(1, 7) , 0);
  58. /*
  59. * KSZ9021 PHY needs at least 10 mSec after PHY reset
  60. * is released to stabilize
  61. */
  62. mdelay(10);
  63. }
  64. static int setup_fec_clock(void)
  65. {
  66. struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  67. /* set gpr1[21] to select anatop clock */
  68. clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, 0x1 << 21);
  69. return enable_fec_anatop_clock(0, ENET_50MHZ);
  70. }
  71. int board_eth_init(bd_t *bis)
  72. {
  73. uint32_t base = IMX_FEC_BASE;
  74. struct mii_dev *bus = NULL;
  75. struct phy_device *phydev = NULL;
  76. gpio_request(IMX_GPIO_NR(5, 0), "PHY-reset");
  77. gpio_request(IMX_GPIO_NR(1, 7), "VIO");
  78. setup_fec_clock();
  79. eth_phy_reset();
  80. bus = fec_get_miibus(base, -1);
  81. if (!bus)
  82. return -EINVAL;
  83. /* Scan PHY 0 */
  84. phydev = phy_find_by_mask(bus, 0xf, PHY_INTERFACE_MODE_RGMII);
  85. if (!phydev) {
  86. printf("Ethernet PHY not found!\n");
  87. return -EINVAL;
  88. }
  89. return fec_probe(bis, -1, base, bus, phydev);
  90. }
  91. #endif
  92. #ifdef CONFIG_USB_EHCI_MX6
  93. static void setup_usb(void)
  94. {
  95. /*
  96. * Set daisy chain for otg_pin_id on MX6Q.
  97. * For MX6DL, this bit is reserved.
  98. */
  99. imx_iomux_set_gpr_register(1, 13, 1, 0);
  100. }
  101. int board_usb_phy_mode(int port)
  102. {
  103. if (port == 1)
  104. return USB_INIT_HOST;
  105. else
  106. return USB_INIT_DEVICE;
  107. }
  108. #endif
  109. static int setup_dhcom_mac_from_fuse(void)
  110. {
  111. struct udevice *dev;
  112. ofnode eeprom;
  113. unsigned char enetaddr[6];
  114. int ret;
  115. ret = eth_env_get_enetaddr("ethaddr", enetaddr);
  116. if (ret) /* ethaddr is already set */
  117. return 0;
  118. imx_get_mac_from_fuse(0, enetaddr);
  119. if (is_valid_ethaddr(enetaddr)) {
  120. eth_env_set_enetaddr("ethaddr", enetaddr);
  121. return 0;
  122. }
  123. eeprom = ofnode_path("/soc/aips-bus@2100000/i2c@21a8000/eeprom@50");
  124. if (!ofnode_valid(eeprom)) {
  125. printf("Invalid hardware path to EEPROM!\n");
  126. return -ENODEV;
  127. }
  128. ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev);
  129. if (ret) {
  130. printf("Cannot find EEPROM!\n");
  131. return ret;
  132. }
  133. ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
  134. if (ret) {
  135. printf("Error reading configuration EEPROM!\n");
  136. return ret;
  137. }
  138. if (is_valid_ethaddr(enetaddr))
  139. eth_env_set_enetaddr("ethaddr", enetaddr);
  140. return 0;
  141. }
  142. int board_early_init_f(void)
  143. {
  144. #ifdef CONFIG_USB_EHCI_MX6
  145. setup_usb();
  146. #endif
  147. return 0;
  148. }
  149. int board_init(void)
  150. {
  151. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  152. /* address of boot parameters */
  153. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  154. /* Enable eim_slow clocks */
  155. setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
  156. setup_dhcom_mac_from_fuse();
  157. return 0;
  158. }
  159. #ifdef CONFIG_CMD_BMODE
  160. static const struct boot_mode board_boot_modes[] = {
  161. /* 4 bit bus width */
  162. {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  163. {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  164. /* 8 bit bus width */
  165. {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
  166. {NULL, 0},
  167. };
  168. #endif
  169. #define HW_CODE_BIT_0 IMX_GPIO_NR(2, 19)
  170. #define HW_CODE_BIT_1 IMX_GPIO_NR(6, 6)
  171. #define HW_CODE_BIT_2 IMX_GPIO_NR(2, 16)
  172. static int board_get_hwcode(void)
  173. {
  174. int hw_code;
  175. gpio_request(HW_CODE_BIT_0, "HW-code-bit-0");
  176. gpio_request(HW_CODE_BIT_1, "HW-code-bit-1");
  177. gpio_request(HW_CODE_BIT_2, "HW-code-bit-2");
  178. gpio_direction_input(HW_CODE_BIT_0);
  179. gpio_direction_input(HW_CODE_BIT_1);
  180. gpio_direction_input(HW_CODE_BIT_2);
  181. /* HW 100 + HW 200 = 00b; HW 300 = 01b */
  182. hw_code = ((gpio_get_value(HW_CODE_BIT_2) << 2) |
  183. (gpio_get_value(HW_CODE_BIT_1) << 1) |
  184. gpio_get_value(HW_CODE_BIT_0)) + 2;
  185. return hw_code;
  186. }
  187. int board_late_init(void)
  188. {
  189. u32 hw_code;
  190. char buf[16];
  191. hw_code = board_get_hwcode();
  192. switch (get_cpu_type()) {
  193. case MXC_CPU_MX6SOLO:
  194. snprintf(buf, sizeof(buf), "imx6s-dhcom%1d", hw_code);
  195. break;
  196. case MXC_CPU_MX6DL:
  197. snprintf(buf, sizeof(buf), "imx6dl-dhcom%1d", hw_code);
  198. break;
  199. case MXC_CPU_MX6D:
  200. snprintf(buf, sizeof(buf), "imx6d-dhcom%1d", hw_code);
  201. break;
  202. case MXC_CPU_MX6Q:
  203. snprintf(buf, sizeof(buf), "imx6q-dhcom%1d", hw_code);
  204. break;
  205. default:
  206. snprintf(buf, sizeof(buf), "UNKNOWN%1d", hw_code);
  207. break;
  208. }
  209. env_set("dhcom", buf);
  210. #ifdef CONFIG_CMD_BMODE
  211. add_board_boot_modes(board_boot_modes);
  212. #endif
  213. return 0;
  214. }
  215. int checkboard(void)
  216. {
  217. puts("Board: DHCOM i.MX6\n");
  218. return 0;
  219. }
  220. #ifdef CONFIG_MULTI_DTB_FIT
  221. int board_fit_config_name_match(const char *name)
  222. {
  223. if (is_mx6dq()) {
  224. if (!strcmp(name, "imx6q-dhcom-pdk2"))
  225. return 0;
  226. } else if (is_mx6sdl()) {
  227. if (!strcmp(name, "imx6dl-dhcom-pdk2"))
  228. return 0;
  229. }
  230. return -1;
  231. }
  232. #endif