board.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * (C) Copyright 2016
  6. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  7. *
  8. * Based on:
  9. * Board functions for TI AM335X based boards
  10. *
  11. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  12. */
  13. #include <common.h>
  14. #include <env.h>
  15. #include <errno.h>
  16. #include <init.h>
  17. #include <irq_func.h>
  18. #include <spl.h>
  19. #include <asm/arch/cpu.h>
  20. #include <asm/arch/hardware.h>
  21. #include <asm/arch/omap.h>
  22. #include <asm/arch/ddr_defs.h>
  23. #include <asm/arch/clock.h>
  24. #include <asm/arch/gpio.h>
  25. #include <asm/arch/mmc_host_def.h>
  26. #include <asm/arch/sys_proto.h>
  27. #include <asm/arch/mem.h>
  28. #include <asm/io.h>
  29. #include <asm/emif.h>
  30. #include <asm/gpio.h>
  31. #include <i2c.h>
  32. #include <miiphy.h>
  33. #include <cpsw.h>
  34. #include <power/tps65217.h>
  35. #include <env_internal.h>
  36. #include <watchdog.h>
  37. #include "mmc.h"
  38. #include "board.h"
  39. DECLARE_GLOBAL_DATA_PTR;
  40. static struct shc_eeprom __attribute__((section(".data"))) header;
  41. static int shc_eeprom_valid;
  42. /*
  43. * Read header information from EEPROM into global structure.
  44. */
  45. static int read_eeprom(void)
  46. {
  47. /* Check if baseboard eeprom is available */
  48. if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
  49. puts("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
  50. return -ENODEV;
  51. }
  52. /* read the eeprom using i2c */
  53. if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
  54. sizeof(header))) {
  55. puts("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n");
  56. return -EIO;
  57. }
  58. if (header.magic != HDR_MAGIC) {
  59. printf("Incorrect magic number (0x%x) in EEPROM\n",
  60. header.magic);
  61. return -EIO;
  62. }
  63. shc_eeprom_valid = 1;
  64. return 0;
  65. }
  66. static void shc_request_gpio(void)
  67. {
  68. gpio_request(LED_PWR_BL_GPIO, "LED PWR BL");
  69. gpio_request(LED_PWR_RD_GPIO, "LED PWR RD");
  70. gpio_request(RESET_GPIO, "reset");
  71. gpio_request(WIFI_REGEN_GPIO, "WIFI REGEN");
  72. gpio_request(WIFI_RST_GPIO, "WIFI rst");
  73. gpio_request(ZIGBEE_RST_GPIO, "ZigBee rst");
  74. gpio_request(BIDCOS_RST_GPIO, "BIDCOS rst");
  75. gpio_request(ENOC_RST_GPIO, "ENOC rst");
  76. #if defined CONFIG_B_SAMPLE
  77. gpio_request(LED_PWR_GN_GPIO, "LED PWR GN");
  78. gpio_request(LED_CONN_BL_GPIO, "LED CONN BL");
  79. gpio_request(LED_CONN_RD_GPIO, "LED CONN RD");
  80. gpio_request(LED_CONN_GN_GPIO, "LED CONN GN");
  81. #else
  82. gpio_request(LED_LAN_BL_GPIO, "LED LAN BL");
  83. gpio_request(LED_LAN_RD_GPIO, "LED LAN RD");
  84. gpio_request(LED_CLOUD_BL_GPIO, "LED CLOUD BL");
  85. gpio_request(LED_CLOUD_RD_GPIO, "LED CLOUD RD");
  86. gpio_request(LED_PWM_GPIO, "LED PWM");
  87. gpio_request(Z_WAVE_RST_GPIO, "Z WAVE rst");
  88. #endif
  89. gpio_request(BACK_BUTTON_GPIO, "Back button");
  90. gpio_request(FRONT_BUTTON_GPIO, "Front button");
  91. }
  92. /*
  93. * Function which forces all installed modules into running state for ICT
  94. * testing. Called by SPL.
  95. */
  96. static void __maybe_unused force_modules_running(void)
  97. {
  98. /* Wi-Fi power regulator enable - high = enabled */
  99. gpio_direction_output(WIFI_REGEN_GPIO, 1);
  100. /*
  101. * Wait for Wi-Fi power regulator to reach a stable voltage
  102. * (soft-start time, max. 350 µs)
  103. */
  104. __udelay(350);
  105. /* Wi-Fi module reset - high = running */
  106. gpio_direction_output(WIFI_RST_GPIO, 1);
  107. /* ZigBee reset - high = running */
  108. gpio_direction_output(ZIGBEE_RST_GPIO, 1);
  109. /* BidCos reset - high = running */
  110. gpio_direction_output(BIDCOS_RST_GPIO, 1);
  111. #if !defined(CONFIG_B_SAMPLE)
  112. /* Z-Wave reset - high = running */
  113. gpio_direction_output(Z_WAVE_RST_GPIO, 1);
  114. #endif
  115. /* EnOcean reset - low = running */
  116. gpio_direction_output(ENOC_RST_GPIO, 0);
  117. }
  118. /*
  119. * Function which forces all installed modules into reset - to be released by
  120. * the OS, called by SPL
  121. */
  122. static void __maybe_unused force_modules_reset(void)
  123. {
  124. /* Wi-Fi module reset - low = reset */
  125. gpio_direction_output(WIFI_RST_GPIO, 0);
  126. /* Wi-Fi power regulator enable - low = disabled */
  127. gpio_direction_output(WIFI_REGEN_GPIO, 0);
  128. /* ZigBee reset - low = reset */
  129. gpio_direction_output(ZIGBEE_RST_GPIO, 0);
  130. /* BidCos reset - low = reset */
  131. /*gpio_direction_output(BIDCOS_RST_GPIO, 0);*/
  132. #if !defined(CONFIG_B_SAMPLE)
  133. /* Z-Wave reset - low = reset */
  134. gpio_direction_output(Z_WAVE_RST_GPIO, 0);
  135. #endif
  136. /* EnOcean reset - high = reset*/
  137. gpio_direction_output(ENOC_RST_GPIO, 1);
  138. }
  139. /*
  140. * Function to set the LEDs in the state "Bootloader booting"
  141. */
  142. static void __maybe_unused leds_set_booting(void)
  143. {
  144. #if defined(CONFIG_B_SAMPLE)
  145. /* Turn all red LEDs on */
  146. gpio_direction_output(LED_PWR_RD_GPIO, 1);
  147. gpio_direction_output(LED_CONN_RD_GPIO, 1);
  148. #else /* All other SHCs starting with B2-Sample */
  149. /* Set the PWM GPIO */
  150. gpio_direction_output(LED_PWM_GPIO, 1);
  151. /* Turn all red LEDs on */
  152. gpio_direction_output(LED_PWR_RD_GPIO, 1);
  153. gpio_direction_output(LED_LAN_RD_GPIO, 1);
  154. gpio_direction_output(LED_CLOUD_RD_GPIO, 1);
  155. #endif
  156. }
  157. /*
  158. * Function to set the LEDs in the state "Bootloader error"
  159. */
  160. static void leds_set_failure(int state)
  161. {
  162. #if defined(CONFIG_B_SAMPLE)
  163. /* Turn all blue and green LEDs off */
  164. gpio_set_value(LED_PWR_BL_GPIO, 0);
  165. gpio_set_value(LED_PWR_GN_GPIO, 0);
  166. gpio_set_value(LED_CONN_BL_GPIO, 0);
  167. gpio_set_value(LED_CONN_GN_GPIO, 0);
  168. /* Turn all red LEDs to 'state' */
  169. gpio_set_value(LED_PWR_RD_GPIO, state);
  170. gpio_set_value(LED_CONN_RD_GPIO, state);
  171. #else /* All other SHCs starting with B2-Sample */
  172. /* Set the PWM GPIO */
  173. gpio_direction_output(LED_PWM_GPIO, 1);
  174. /* Turn all blue LEDs off */
  175. gpio_set_value(LED_PWR_BL_GPIO, 0);
  176. gpio_set_value(LED_LAN_BL_GPIO, 0);
  177. gpio_set_value(LED_CLOUD_BL_GPIO, 0);
  178. /* Turn all red LEDs to 'state' */
  179. gpio_set_value(LED_PWR_RD_GPIO, state);
  180. gpio_set_value(LED_LAN_RD_GPIO, state);
  181. gpio_set_value(LED_CLOUD_RD_GPIO, state);
  182. #endif
  183. }
  184. /*
  185. * Function to set the LEDs in the state "Bootloader finished"
  186. */
  187. static void leds_set_finish(void)
  188. {
  189. #if defined(CONFIG_B_SAMPLE)
  190. /* Turn all LEDs off */
  191. gpio_set_value(LED_PWR_BL_GPIO, 0);
  192. gpio_set_value(LED_PWR_RD_GPIO, 0);
  193. gpio_set_value(LED_PWR_GN_GPIO, 0);
  194. gpio_set_value(LED_CONN_BL_GPIO, 0);
  195. gpio_set_value(LED_CONN_RD_GPIO, 0);
  196. gpio_set_value(LED_CONN_GN_GPIO, 0);
  197. #else /* All other SHCs starting with B2-Sample */
  198. /* Turn all LEDs off */
  199. gpio_set_value(LED_PWR_BL_GPIO, 0);
  200. gpio_set_value(LED_PWR_RD_GPIO, 0);
  201. gpio_set_value(LED_LAN_BL_GPIO, 0);
  202. gpio_set_value(LED_LAN_RD_GPIO, 0);
  203. gpio_set_value(LED_CLOUD_BL_GPIO, 0);
  204. gpio_set_value(LED_CLOUD_RD_GPIO, 0);
  205. /* Turn off the PWM GPIO and mux it to EHRPWM */
  206. gpio_set_value(LED_PWM_GPIO, 0);
  207. enable_shc_board_pwm_pin_mux();
  208. #endif
  209. }
  210. static void check_button_status(void)
  211. {
  212. ulong value;
  213. gpio_direction_input(FRONT_BUTTON_GPIO);
  214. value = gpio_get_value(FRONT_BUTTON_GPIO);
  215. if (value == 0) {
  216. printf("front button activated !\n");
  217. env_set("harakiri", "1");
  218. }
  219. }
  220. #if defined(CONFIG_SPL_BUILD)
  221. #ifdef CONFIG_SPL_OS_BOOT
  222. int spl_start_uboot(void)
  223. {
  224. return 1;
  225. }
  226. #endif
  227. static void shc_board_early_init(void)
  228. {
  229. shc_request_gpio();
  230. # ifdef CONFIG_SHC_ICT
  231. /* Force all modules into enabled state for ICT testing */
  232. force_modules_running();
  233. # else
  234. /* Force all modules to enter Reset state until released by the OS */
  235. force_modules_reset();
  236. # endif
  237. leds_set_booting();
  238. }
  239. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  240. #define MPU_SPREADING_PERMILLE 18 /* Spread 1.8 percent */
  241. #define OSC (V_OSCK/1000000)
  242. /* Bosch: Predivider must be fixed to 4, so N = 4-1 */
  243. #define MPUPLL_N (4-1)
  244. /* Bosch: Fref = 24 MHz / (N+1) = 24 MHz / 4 = 6 MHz */
  245. #define MPUPLL_FREF (OSC / (MPUPLL_N + 1))
  246. const struct dpll_params dpll_ddr_shc = {
  247. 400, OSC-1, 1, -1, -1, -1, -1};
  248. const struct dpll_params *get_dpll_ddr_params(void)
  249. {
  250. return &dpll_ddr_shc;
  251. }
  252. /*
  253. * As we enabled downspread SSC with 1.8%, the values needed to be corrected
  254. * such that the 20% overshoot will not lead to too high frequencies.
  255. * In all cases, this is achieved by subtracting one from M (6 MHz less).
  256. * Example: 600 MHz CPU
  257. * Step size: 24 MHz OSC, N = 4 (fix) --> Fref = 6 MHz
  258. * 600 MHz - 6 MHz (1x Fref) = 594 MHz
  259. * SSC: 594 MHz * 1.8% = 10.7 MHz SSC
  260. * Overshoot: 10.7 MHz * 20 % = 2.2 MHz
  261. * --> Fmax = 594 MHz + 2.2 MHz = 596.2 MHz, lower than 600 MHz --> OK!
  262. */
  263. const struct dpll_params dpll_mpu_shc_opp100 = {
  264. 99, MPUPLL_N, 1, -1, -1, -1, -1};
  265. void am33xx_spl_board_init(void)
  266. {
  267. int sil_rev;
  268. int mpu_vdd;
  269. puts(BOARD_ID_STR);
  270. /*
  271. * Set CORE Frequency to OPP100
  272. * Hint: DCDC3 (CORE) defaults to 1.100V (for OPP100)
  273. */
  274. do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
  275. sil_rev = readl(&cdev->deviceid) >> 28;
  276. if (sil_rev < 2) {
  277. puts("We do not support Silicon Revisions below 2.0!\n");
  278. return;
  279. }
  280. dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
  281. if (i2c_probe(TPS65217_CHIP_PM))
  282. return;
  283. /*
  284. * Retrieve the CPU max frequency by reading the efuse
  285. * SHC-Default: 600 MHz
  286. */
  287. switch (dpll_mpu_opp100.m) {
  288. case MPUPLL_M_1000:
  289. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
  290. break;
  291. case MPUPLL_M_800:
  292. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
  293. break;
  294. case MPUPLL_M_720:
  295. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
  296. break;
  297. case MPUPLL_M_600:
  298. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
  299. break;
  300. case MPUPLL_M_300:
  301. mpu_vdd = TPS65217_DCDC_VOLT_SEL_950MV;
  302. break;
  303. default:
  304. puts("Cannot determine the frequency, failing!\n");
  305. return;
  306. }
  307. if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
  308. puts("tps65217_voltage_update failure\n");
  309. return;
  310. }
  311. /* Set MPU Frequency to what we detected */
  312. printf("MPU reference clock runs at %d MHz\n", MPUPLL_FREF);
  313. printf("Setting MPU clock to %d MHz\n", MPUPLL_FREF *
  314. dpll_mpu_shc_opp100.m);
  315. do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_shc_opp100);
  316. /* Enable Spread Spectrum for this freq to be clean on EMI side */
  317. set_mpu_spreadspectrum(MPU_SPREADING_PERMILLE);
  318. /*
  319. * Using the default voltages for the PMIC (TPS65217D)
  320. * LS1 = 1.8V (VDD_1V8)
  321. * LS2 = 3.3V (VDD_3V3A)
  322. * LDO1 = 1.8V (VIO and VRTC)
  323. * LDO2 = 3.3V (VDD_3V3AUX)
  324. */
  325. shc_board_early_init();
  326. }
  327. void set_uart_mux_conf(void)
  328. {
  329. enable_uart0_pin_mux();
  330. }
  331. void set_mux_conf_regs(void)
  332. {
  333. enable_shc_board_pin_mux();
  334. }
  335. const struct ctrl_ioregs ioregs_evmsk = {
  336. .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  337. .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  338. .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  339. .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  340. .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  341. };
  342. static const struct ddr_data ddr3_shc_data = {
  343. .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  344. .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  345. .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  346. .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  347. };
  348. static const struct cmd_control ddr3_shc_cmd_ctrl_data = {
  349. .cmd0csratio = MT41K256M16HA125E_RATIO,
  350. .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  351. .cmd1csratio = MT41K256M16HA125E_RATIO,
  352. .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  353. .cmd2csratio = MT41K256M16HA125E_RATIO,
  354. .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  355. };
  356. static struct emif_regs ddr3_shc_emif_reg_data = {
  357. .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  358. .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  359. .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  360. .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  361. .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  362. .zq_config = MT41K256M16HA125E_ZQ_CFG,
  363. .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
  364. PHY_EN_DYN_PWRDN,
  365. };
  366. void sdram_init(void)
  367. {
  368. /* Configure the DDR3 RAM */
  369. config_ddr(400, &ioregs_evmsk, &ddr3_shc_data,
  370. &ddr3_shc_cmd_ctrl_data, &ddr3_shc_emif_reg_data, 0);
  371. }
  372. #endif
  373. /*
  374. * Basic board specific setup. Pinmux has been handled already.
  375. */
  376. int board_init(void)
  377. {
  378. #if defined(CONFIG_HW_WATCHDOG)
  379. hw_watchdog_init();
  380. #endif
  381. i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  382. if (read_eeprom() < 0)
  383. puts("EEPROM Content Invalid.\n");
  384. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  385. #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
  386. gpmc_init();
  387. #endif
  388. shc_request_gpio();
  389. return 0;
  390. }
  391. #ifdef CONFIG_BOARD_LATE_INIT
  392. int board_late_init(void)
  393. {
  394. check_button_status();
  395. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  396. if (shc_eeprom_valid)
  397. if (is_valid_ethaddr(header.mac_addr))
  398. eth_env_set_enetaddr("ethaddr", header.mac_addr);
  399. #endif
  400. return 0;
  401. }
  402. #endif
  403. #if defined(CONFIG_USB_ETHER) && \
  404. (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER))
  405. int board_eth_init(bd_t *bis)
  406. {
  407. return usb_eth_initialize(bis);
  408. }
  409. #endif
  410. #ifdef CONFIG_SHOW_BOOT_PROGRESS
  411. static void bosch_check_reset_pin(void)
  412. {
  413. if (readl(GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0) & RESET_MASK) {
  414. printf("Resetting ...\n");
  415. writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0);
  416. disable_interrupts();
  417. reset_cpu(0);
  418. /*NOTREACHED*/
  419. }
  420. }
  421. static void hang_bosch(const char *cause, int code)
  422. {
  423. int lv;
  424. gpio_direction_input(RESET_GPIO);
  425. /* Enable reset pin interrupt on falling edge */
  426. writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0);
  427. writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_FALLINGDETECT);
  428. enable_interrupts();
  429. puts(cause);
  430. for (;;) {
  431. for (lv = 0; lv < code; lv++) {
  432. bosch_check_reset_pin();
  433. leds_set_failure(1);
  434. __udelay(150 * 1000);
  435. leds_set_failure(0);
  436. __udelay(150 * 1000);
  437. }
  438. #if defined(BLINK_CODE)
  439. __udelay(300 * 1000);
  440. #endif
  441. }
  442. }
  443. void show_boot_progress(int val)
  444. {
  445. switch (val) {
  446. case BOOTSTAGE_ID_NEED_RESET:
  447. hang_bosch("need reset", 4);
  448. break;
  449. }
  450. }
  451. void arch_preboot_os(void)
  452. {
  453. leds_set_finish();
  454. }
  455. #endif