gurnard.c 10 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Bluewater Systems Snapper 9260/9G20 modules
  4. *
  5. * (C) Copyright 2011 Bluewater Systems
  6. * Author: Andre Renaud <andre@bluewatersys.com>
  7. * Author: Ryan Mallon <ryan@bluewatersys.com>
  8. */
  9. #include <common.h>
  10. #include <atmel_lcd.h>
  11. #include <atmel_lcdc.h>
  12. #include <atmel_mci.h>
  13. #include <dm.h>
  14. #include <env.h>
  15. #include <init.h>
  16. #include <lcd.h>
  17. #include <net.h>
  18. #ifndef CONFIG_DM_ETH
  19. #include <netdev.h>
  20. #endif
  21. #include <asm/gpio.h>
  22. #include <asm/io.h>
  23. #include <asm/mach-types.h>
  24. #include <asm/arch/at91sam9g45_matrix.h>
  25. #include <asm/arch/at91sam9_smc.h>
  26. #include <asm/arch/at91_common.h>
  27. #include <asm/arch/at91_emac.h>
  28. #include <asm/arch/at91_rstc.h>
  29. #include <asm/arch/at91_rtc.h>
  30. #include <asm/arch/at91_sck.h>
  31. #include <asm/arch/atmel_serial.h>
  32. #include <asm/arch/clk.h>
  33. #include <asm/arch/gpio.h>
  34. #include <dm/uclass-internal.h>
  35. #ifdef CONFIG_GURNARD_SPLASH
  36. #include "splash_logo.h"
  37. #endif
  38. DECLARE_GLOBAL_DATA_PTR;
  39. /* IO Expander pins */
  40. #define IO_EXP_ETH_RESET (0 << 1)
  41. #define IO_EXP_ETH_POWER (1 << 1)
  42. #ifdef CONFIG_MACB
  43. static void gurnard_macb_hw_init(void)
  44. {
  45. struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
  46. at91_periph_clk_enable(ATMEL_ID_EMAC);
  47. /*
  48. * Enable pull-up on:
  49. * RXDV (PA12) => MODE0 - PHY also has pull-up
  50. * ERX0 (PA13) => MODE1 - PHY also has pull-up
  51. * ERX1 (PA15) => MODE2 - PHY also has pull-up
  52. */
  53. writel(pin_to_mask(AT91_PIN_PA15) |
  54. pin_to_mask(AT91_PIN_PA12) |
  55. pin_to_mask(AT91_PIN_PA13),
  56. &pioa->puer);
  57. at91_phy_reset();
  58. at91_macb_hw_init();
  59. }
  60. #endif
  61. #ifdef CONFIG_CMD_NAND
  62. static int gurnard_nand_hw_init(void)
  63. {
  64. struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  65. struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  66. ulong flags;
  67. int ret;
  68. /* Enable CS3 as NAND/SmartMedia */
  69. setbits_le32(&matrix->ebicsa, AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
  70. /* Configure SMC CS3 for NAND/SmartMedia */
  71. writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
  72. AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
  73. &smc->cs[3].setup);
  74. writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
  75. AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
  76. &smc->cs[3].pulse);
  77. writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
  78. &smc->cs[3].cycle);
  79. #ifdef CONFIG_SYS_NAND_DBW_16
  80. flags = AT91_SMC_MODE_DBW_16;
  81. #else
  82. flags = AT91_SMC_MODE_DBW_8;
  83. #endif
  84. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  85. AT91_SMC_MODE_EXNW_DISABLE |
  86. flags |
  87. AT91_SMC_MODE_TDF_CYCLE(3),
  88. &smc->cs[3].mode);
  89. ret = gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy");
  90. if (ret)
  91. return ret;
  92. gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
  93. /* Enable NandFlash */
  94. ret = gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce");
  95. if (ret)
  96. return ret;
  97. gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  98. return 0;
  99. }
  100. #endif
  101. #ifdef CONFIG_GURNARD_SPLASH
  102. static void lcd_splash(int width, int height)
  103. {
  104. u16 colour;
  105. int x, y;
  106. u16 *base_addr = (u16 *)gd->video_bottom;
  107. memset(base_addr, 0xff, width * height * 2);
  108. /*
  109. * Blit the logo to the center of the screen
  110. */
  111. for (y = 0; y < BMP_LOGO_HEIGHT; y++) {
  112. for (x = 0; x < BMP_LOGO_WIDTH; x++) {
  113. int posx, posy;
  114. colour = bmp_logo_palette[bmp_logo_bitmap[
  115. y * BMP_LOGO_WIDTH + x]];
  116. posx = x + (width - BMP_LOGO_WIDTH) / 2;
  117. posy = y;
  118. base_addr[posy * width + posx] = colour;
  119. }
  120. }
  121. }
  122. #endif
  123. #ifdef CONFIG_DM_VIDEO
  124. static void at91sam9g45_lcd_hw_init(void)
  125. {
  126. at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
  127. at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
  128. at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
  129. at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
  130. at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
  131. at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
  132. at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
  133. at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
  134. at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
  135. at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
  136. at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
  137. at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
  138. at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
  139. at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
  140. at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
  141. at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
  142. at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
  143. at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
  144. at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */
  145. at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
  146. at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
  147. at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
  148. at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
  149. at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
  150. at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
  151. at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
  152. at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */
  153. at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
  154. at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
  155. at91_periph_clk_enable(ATMEL_ID_LCDC);
  156. }
  157. #endif
  158. #ifdef CONFIG_GURNARD_FPGA
  159. /**
  160. * Initialise the memory bus settings so that we can talk to the
  161. * memory mapped FPGA
  162. */
  163. static int fpga_hw_init(void)
  164. {
  165. struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  166. struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  167. int i;
  168. setbits_le32(&matrix->ebicsa, AT91_MATRIX_EBI_CS1A_SDRAMC);
  169. at91_set_a_periph(2, 4, 0); /* EBIA21 */
  170. at91_set_a_periph(2, 5, 0); /* EBIA22 */
  171. at91_set_a_periph(2, 6, 0); /* EBIA23 */
  172. at91_set_a_periph(2, 7, 0); /* EBIA24 */
  173. at91_set_a_periph(2, 12, 0); /* EBIA25 */
  174. for (i = 15; i <= 31; i++) /* EBINWAIT & EBID16 - 31 */
  175. at91_set_a_periph(2, i, 0);
  176. /* configure SMC cs0 for FPGA access timing */
  177. writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(2) |
  178. AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(2),
  179. &smc->cs[0].setup);
  180. writel(AT91_SMC_PULSE_NWE(5) | AT91_SMC_PULSE_NCS_WR(4) |
  181. AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(4),
  182. &smc->cs[0].pulse);
  183. writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
  184. &smc->cs[0].cycle);
  185. writel(AT91_SMC_MODE_BAT |
  186. AT91_SMC_MODE_EXNW_DISABLE |
  187. AT91_SMC_MODE_DBW_32 |
  188. AT91_SMC_MODE_TDF |
  189. AT91_SMC_MODE_TDF_CYCLE(2),
  190. &smc->cs[0].mode);
  191. /* Do a write to within EBI_CS1 to enable the SDCK */
  192. writel(0, ATMEL_BASE_CS1);
  193. return 0;
  194. }
  195. #endif
  196. #ifdef CONFIG_CMD_USB
  197. #define USB0_ENABLE_PIN AT91_PIN_PB22
  198. #define USB1_ENABLE_PIN AT91_PIN_PB23
  199. void gurnard_usb_init(void)
  200. {
  201. at91_set_gpio_output(USB0_ENABLE_PIN, 1);
  202. at91_set_gpio_value(USB0_ENABLE_PIN, 0);
  203. at91_set_gpio_output(USB1_ENABLE_PIN, 1);
  204. at91_set_gpio_value(USB1_ENABLE_PIN, 0);
  205. }
  206. #endif
  207. #ifdef CONFIG_GENERIC_ATMEL_MCI
  208. int cpu_mmc_init(bd_t *bis)
  209. {
  210. return atmel_mci_init((void *)ATMEL_BASE_MCI0);
  211. }
  212. #endif
  213. static void gurnard_enable_console(int enable)
  214. {
  215. at91_set_gpio_output(AT91_PIN_PB14, 1);
  216. at91_set_gpio_value(AT91_PIN_PB14, enable ? 0 : 1);
  217. }
  218. void at91sam9g45_slowclock_init(void)
  219. {
  220. /*
  221. * On AT91SAM9G45 revC CPUs, the slow clock can be based on an
  222. * internal impreciseRC oscillator or an external 32kHz oscillator.
  223. * Switch to the latter.
  224. */
  225. unsigned i, tmp;
  226. ulong *reg = (ulong *)ATMEL_BASE_SCKCR;
  227. tmp = readl(reg);
  228. if ((tmp & AT91SAM9G45_SCKCR_OSCSEL) == AT91SAM9G45_SCKCR_OSCSEL_RC) {
  229. timer_init();
  230. tmp |= AT91SAM9G45_SCKCR_OSC32EN;
  231. writel(tmp, reg);
  232. for (i = 0; i < 1200; i++)
  233. udelay(1000);
  234. tmp |= AT91SAM9G45_SCKCR_OSCSEL_32;
  235. writel(tmp, reg);
  236. udelay(200);
  237. tmp &= ~AT91SAM9G45_SCKCR_RCEN;
  238. writel(tmp, reg);
  239. }
  240. }
  241. int board_early_init_f(void)
  242. {
  243. at91_seriald_hw_init();
  244. gurnard_enable_console(1);
  245. return 0;
  246. }
  247. int board_init(void)
  248. {
  249. const char *rev_str;
  250. #ifdef CONFIG_CMD_NAND
  251. int ret;
  252. #endif
  253. at91_periph_clk_enable(ATMEL_ID_PIOA);
  254. at91_periph_clk_enable(ATMEL_ID_PIOB);
  255. at91_periph_clk_enable(ATMEL_ID_PIOC);
  256. at91_periph_clk_enable(ATMEL_ID_PIODE);
  257. at91sam9g45_slowclock_init();
  258. /*
  259. * Clear the RTC IDR to disable all IRQs. Avoid issues when Linux
  260. * boots with spurious IRQs.
  261. */
  262. writel(0xffffffff, AT91_RTC_IDR);
  263. /* Make sure that the reset signal is attached properly */
  264. setbits_le32(AT91_ASM_RSTC_MR, AT91_RSTC_KEY | AT91_RSTC_MR_URSTEN);
  265. gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260;
  266. /* Address of boot parameters */
  267. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  268. #ifdef CONFIG_CMD_NAND
  269. ret = gurnard_nand_hw_init();
  270. if (ret)
  271. return ret;
  272. #endif
  273. #ifdef CONFIG_ATMEL_SPI
  274. at91_spi0_hw_init(1 << 4);
  275. #endif
  276. #ifdef CONFIG_MACB
  277. gurnard_macb_hw_init();
  278. #endif
  279. #ifdef CONFIG_GURNARD_FPGA
  280. fpga_hw_init();
  281. #endif
  282. #ifdef CONFIG_CMD_USB
  283. gurnard_usb_init();
  284. #endif
  285. #ifdef CONFIG_CMD_MMC
  286. at91_set_A_periph(AT91_PIN_PA12, 0);
  287. at91_set_gpio_output(AT91_PIN_PA8, 1);
  288. at91_set_gpio_value(AT91_PIN_PA8, 0);
  289. at91_mci_hw_init();
  290. #endif
  291. #ifdef CONFIG_DM_VIDEO
  292. at91sam9g45_lcd_hw_init();
  293. at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */
  294. /* Select the second timing index for board rev 2 */
  295. rev_str = env_get("board_rev");
  296. if (rev_str && !strncmp(rev_str, "2", 1)) {
  297. struct udevice *dev;
  298. uclass_find_first_device(UCLASS_VIDEO, &dev);
  299. if (dev) {
  300. struct atmel_lcd_platdata *plat = dev_get_platdata(dev);
  301. plat->timing_index = 1;
  302. }
  303. }
  304. #endif
  305. return 0;
  306. }
  307. int board_late_init(void)
  308. {
  309. u_int8_t env_enetaddr[8];
  310. char *env_str;
  311. char *end;
  312. int i;
  313. /*
  314. * Set MAC address so we do not need to init Ethernet before Linux
  315. * boot
  316. */
  317. env_str = env_get("ethaddr");
  318. if (env_str) {
  319. struct at91_emac *emac = (struct at91_emac *)ATMEL_BASE_EMAC;
  320. /* Parse MAC address */
  321. for (i = 0; i < 6; i++) {
  322. env_enetaddr[i] = env_str ?
  323. simple_strtoul(env_str, &end, 16) : 0;
  324. if (env_str)
  325. env_str = (*end) ? end+1 : end;
  326. }
  327. /* Set hardware address */
  328. writel(env_enetaddr[0] | env_enetaddr[1] << 8 |
  329. env_enetaddr[2] << 16 | env_enetaddr[3] << 24,
  330. &emac->sa2l);
  331. writel((env_enetaddr[4] | env_enetaddr[5] << 8), &emac->sa2h);
  332. printf("MAC: %s\n", env_get("ethaddr"));
  333. } else {
  334. /* Not set in environment */
  335. printf("MAC: not set\n");
  336. }
  337. #ifdef CONFIG_GURNARD_SPLASH
  338. lcd_splash(480, 272);
  339. #endif
  340. return 0;
  341. }
  342. #ifndef CONFIG_DM_ETH
  343. int board_eth_init(bd_t *bis)
  344. {
  345. return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0);
  346. }
  347. #endif
  348. int dram_init(void)
  349. {
  350. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  351. CONFIG_SYS_SDRAM_SIZE);
  352. return 0;
  353. }
  354. void reset_phy(void)
  355. {
  356. }
  357. static struct atmel_serial_platdata at91sam9260_serial_plat = {
  358. .base_addr = ATMEL_BASE_DBGU,
  359. };
  360. U_BOOT_DEVICE(at91sam9260_serial) = {
  361. .name = "serial_atmel",
  362. .platdata = &at91sam9260_serial_plat,
  363. };