mx53cx9020.c 6.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG
  4. * Patrick Bruenn <p.bruenn@beckhoff.com>
  5. *
  6. * Based on <u-boot>/board/freescale/mx53loco/mx53loco.c
  7. * Copyright (C) 2011 Freescale Semiconductor, Inc.
  8. */
  9. #include <common.h>
  10. #include <cpu_func.h>
  11. #include <init.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/iomux-mx53.h>
  15. #include <asm/mach-imx/mx5_video.h>
  16. #include <ACEX1K.h>
  17. #include <asm/gpio.h>
  18. enum LED_GPIOS {
  19. GPIO_SD1_CD = IMX_GPIO_NR(1, 1),
  20. GPIO_SD2_CD = IMX_GPIO_NR(1, 4),
  21. GPIO_LED_SD2_R = IMX_GPIO_NR(3, 16),
  22. GPIO_LED_SD2_B = IMX_GPIO_NR(3, 17),
  23. GPIO_LED_SD2_G = IMX_GPIO_NR(3, 18),
  24. GPIO_LED_SD1_R = IMX_GPIO_NR(3, 19),
  25. GPIO_LED_SD1_B = IMX_GPIO_NR(3, 20),
  26. GPIO_LED_SD1_G = IMX_GPIO_NR(3, 21),
  27. GPIO_LED_PWR_R = IMX_GPIO_NR(3, 22),
  28. GPIO_LED_PWR_B = IMX_GPIO_NR(3, 23),
  29. GPIO_LED_PWR_G = IMX_GPIO_NR(3, 24),
  30. GPIO_SUPS_INT = IMX_GPIO_NR(3, 31),
  31. GPIO_C3_CONFIG = IMX_GPIO_NR(6, 8),
  32. GPIO_C3_STATUS = IMX_GPIO_NR(6, 7),
  33. GPIO_C3_DONE = IMX_GPIO_NR(6, 9),
  34. };
  35. #define CCAT_BASE_ADDR ((void *)0xf0000000)
  36. #define CCAT_END_ADDR (CCAT_BASE_ADDR + (1024 * 1024 * 32))
  37. #define CCAT_SIZE 1191788
  38. #define CCAT_SIGN_ADDR (CCAT_BASE_ADDR + 12)
  39. static const char CCAT_SIGNATURE[] = "CCAT";
  40. static const u32 CCAT_MODE_CONFIG = 0x0024DC81;
  41. static const u32 CCAT_MODE_RUN = 0x0033DC8F;
  42. DECLARE_GLOBAL_DATA_PTR;
  43. u32 get_board_rev(void)
  44. {
  45. struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
  46. struct fuse_bank *bank = &iim->bank[0];
  47. struct fuse_bank0_regs *fuse =
  48. (struct fuse_bank0_regs *)bank->fuse_regs;
  49. int rev = readl(&fuse->gp[6]);
  50. return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
  51. }
  52. /*
  53. * Set CCAT mode
  54. * @mode: use CCAT_MODE_CONFIG or CCAT_MODE_RUN
  55. */
  56. void weim_cs0_settings(u32 mode)
  57. {
  58. struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
  59. writel(0x0, &weim_regs->cs0gcr1);
  60. writel(mode, &weim_regs->cs0gcr1);
  61. writel(0x00001002, &weim_regs->cs0gcr2);
  62. writel(0x04000000, &weim_regs->cs0rcr1);
  63. writel(0x00000000, &weim_regs->cs0rcr2);
  64. writel(0x04000000, &weim_regs->cs0wcr1);
  65. writel(0x00000000, &weim_regs->cs0wcr2);
  66. }
  67. static void setup_gpio_eim(void)
  68. {
  69. gpio_request(GPIO_C3_STATUS, "GPIO_C3_STATUS");
  70. gpio_request(GPIO_C3_DONE, "GPIO_C3_DONE");
  71. gpio_request(GPIO_C3_CONFIG, "GPIO_C3_CONFIG");
  72. gpio_direction_input(GPIO_C3_STATUS);
  73. gpio_direction_input(GPIO_C3_DONE);
  74. gpio_direction_output(GPIO_C3_CONFIG, 1);
  75. weim_cs0_settings(CCAT_MODE_RUN);
  76. }
  77. static void setup_gpio_sups(void)
  78. {
  79. gpio_request(GPIO_SUPS_INT, "GPIO_SUPS_INT");
  80. gpio_direction_input(GPIO_SUPS_INT);
  81. static const int BLINK_INTERVALL = 50000;
  82. int status = 1;
  83. while (gpio_get_value(GPIO_SUPS_INT)) {
  84. /* signal "CX SUPS power fail" */
  85. gpio_set_value(GPIO_LED_PWR_R,
  86. (++status / BLINK_INTERVALL) % 2);
  87. }
  88. /* signal "CX power up" */
  89. gpio_set_value(GPIO_LED_PWR_R, 1);
  90. }
  91. static void setup_gpio_leds(void)
  92. {
  93. gpio_request(GPIO_LED_SD2_R, "GPIO_LED_SD2_R");
  94. gpio_request(GPIO_LED_SD2_B, "GPIO_LED_SD2_B");
  95. gpio_request(GPIO_LED_SD2_G, "GPIO_LED_SD2_G");
  96. gpio_request(GPIO_LED_SD1_R, "GPIO_LED_SD1_R");
  97. gpio_request(GPIO_LED_SD1_B, "GPIO_LED_SD1_B");
  98. gpio_request(GPIO_LED_SD1_G, "GPIO_LED_SD1_G");
  99. gpio_request(GPIO_LED_PWR_R, "GPIO_LED_PWR_R");
  100. gpio_request(GPIO_LED_PWR_B, "GPIO_LED_PWR_B");
  101. gpio_request(GPIO_LED_PWR_G, "GPIO_LED_PWR_G");
  102. gpio_direction_output(GPIO_LED_SD2_R, 0);
  103. gpio_direction_output(GPIO_LED_SD2_B, 0);
  104. gpio_direction_output(GPIO_LED_SD2_G, 0);
  105. gpio_direction_output(GPIO_LED_SD1_R, 0);
  106. gpio_direction_output(GPIO_LED_SD1_B, 0);
  107. gpio_direction_output(GPIO_LED_SD1_G, 0);
  108. gpio_direction_output(GPIO_LED_PWR_R, 0);
  109. gpio_direction_output(GPIO_LED_PWR_B, 0);
  110. gpio_direction_output(GPIO_LED_PWR_G, 0);
  111. }
  112. #ifdef CONFIG_USB_EHCI_MX5
  113. int board_ehci_hcd_init(int port)
  114. {
  115. /* request VBUS power enable pin, GPIO7_8 */
  116. gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
  117. return 0;
  118. }
  119. #endif
  120. static int power_init(void)
  121. {
  122. /* nothing to do on CX9020 */
  123. return 0;
  124. }
  125. static void clock_1GHz(void)
  126. {
  127. int ret;
  128. u32 ref_clk = MXC_HCLK;
  129. /*
  130. * After increasing voltage to 1.25V, we can switch
  131. * CPU clock to 1GHz and DDR to 400MHz safely
  132. */
  133. ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
  134. if (ret)
  135. printf("CPU: Switch CPU clock to 1GHZ failed\n");
  136. ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
  137. ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
  138. if (ret)
  139. printf("CPU: Switch DDR clock to 400MHz failed\n");
  140. }
  141. int board_early_init_f(void)
  142. {
  143. return 0;
  144. }
  145. int board_init(void)
  146. {
  147. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  148. mxc_set_sata_internal_clock();
  149. setup_gpio_leds();
  150. setup_gpio_sups();
  151. setup_gpio_eim();
  152. setup_iomux_lcd();
  153. return 0;
  154. }
  155. int checkboard(void)
  156. {
  157. puts("Board: Beckhoff CX9020\n");
  158. return 0;
  159. }
  160. static int ccat_config_fn(int assert_config, int flush, int cookie)
  161. {
  162. /* prepare FPGA for programming */
  163. weim_cs0_settings(CCAT_MODE_CONFIG);
  164. gpio_set_value(GPIO_C3_CONFIG, 0);
  165. udelay(1);
  166. gpio_set_value(GPIO_C3_CONFIG, 1);
  167. udelay(230);
  168. return FPGA_SUCCESS;
  169. }
  170. static int ccat_status_fn(int cookie)
  171. {
  172. return FPGA_FAIL;
  173. }
  174. static int ccat_write_fn(const void *buf, size_t buf_len, int flush, int cookie)
  175. {
  176. const uint8_t *const buffer = buf;
  177. /* program CCAT */
  178. int i;
  179. for (i = 0; i < buf_len; ++i)
  180. writeb(buffer[i], CCAT_BASE_ADDR);
  181. writeb(0xff, CCAT_BASE_ADDR);
  182. writeb(0xff, CCAT_BASE_ADDR);
  183. return FPGA_SUCCESS;
  184. }
  185. static int ccat_done_fn(int cookie)
  186. {
  187. /* programming complete? */
  188. return gpio_get_value(GPIO_C3_DONE);
  189. }
  190. static int ccat_post_fn(int cookie)
  191. {
  192. /* switch to FPGA run mode */
  193. weim_cs0_settings(CCAT_MODE_RUN);
  194. invalidate_dcache_range((ulong) CCAT_BASE_ADDR, (ulong) CCAT_END_ADDR);
  195. if (memcmp(CCAT_SIGN_ADDR, CCAT_SIGNATURE, sizeof(CCAT_SIGNATURE))) {
  196. printf("Verifing CCAT firmware failed, signature not found\n");
  197. return FPGA_FAIL;
  198. }
  199. /* signal "CX booting OS" */
  200. gpio_set_value(GPIO_LED_PWR_R, 1);
  201. gpio_set_value(GPIO_LED_PWR_G, 1);
  202. gpio_set_value(GPIO_LED_PWR_B, 0);
  203. return FPGA_SUCCESS;
  204. }
  205. static Altera_CYC2_Passive_Serial_fns ccat_fns = {
  206. .config = ccat_config_fn,
  207. .status = ccat_status_fn,
  208. .done = ccat_done_fn,
  209. .write = ccat_write_fn,
  210. .abort = ccat_post_fn,
  211. .post = ccat_post_fn,
  212. };
  213. static Altera_desc ccat_fpga = {
  214. .family = Altera_CYC2,
  215. .iface = passive_serial,
  216. .size = CCAT_SIZE,
  217. .iface_fns = &ccat_fns,
  218. .base = CCAT_BASE_ADDR,
  219. };
  220. int board_late_init(void)
  221. {
  222. if (!power_init())
  223. clock_1GHz();
  224. fpga_init();
  225. fpga_add(fpga_altera, &ccat_fpga);
  226. return 0;
  227. }