sama5d3_xplained.c 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Atmel Corporation
  4. * Bo Shen <voice.shen@atmel.com>
  5. */
  6. #include <common.h>
  7. #include <init.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/sama5d3_smc.h>
  10. #include <asm/arch/at91_common.h>
  11. #include <asm/arch/at91_rstc.h>
  12. #include <asm/arch/gpio.h>
  13. #include <asm/arch/clk.h>
  14. #include <debug_uart.h>
  15. #include <spl.h>
  16. #include <asm/arch/atmel_mpddrc.h>
  17. #include <asm/arch/at91_wdt.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. extern void at91_pda_detect(void);
  20. #ifdef CONFIG_NAND_ATMEL
  21. void sama5d3_xplained_nand_hw_init(void)
  22. {
  23. struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  24. at91_periph_clk_enable(ATMEL_ID_SMC);
  25. /* Configure SMC CS3 for NAND/SmartMedia */
  26. writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
  27. AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
  28. &smc->cs[3].setup);
  29. writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
  30. AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
  31. &smc->cs[3].pulse);
  32. writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
  33. &smc->cs[3].cycle);
  34. writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
  35. AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) |
  36. AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3)|
  37. AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
  38. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  39. AT91_SMC_MODE_EXNW_DISABLE |
  40. #ifdef CONFIG_SYS_NAND_DBW_16
  41. AT91_SMC_MODE_DBW_16 |
  42. #else /* CONFIG_SYS_NAND_DBW_8 */
  43. AT91_SMC_MODE_DBW_8 |
  44. #endif
  45. AT91_SMC_MODE_TDF_CYCLE(3),
  46. &smc->cs[3].mode);
  47. }
  48. #endif
  49. #ifdef CONFIG_CMD_USB
  50. static void sama5d3_xplained_usb_hw_init(void)
  51. {
  52. at91_set_pio_output(AT91_PIO_PORTE, 3, 0);
  53. at91_set_pio_output(AT91_PIO_PORTE, 4, 0);
  54. }
  55. #endif
  56. #ifdef CONFIG_GENERIC_ATMEL_MCI
  57. static void sama5d3_xplained_mci0_hw_init(void)
  58. {
  59. at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* MCI0 Power */
  60. }
  61. #endif
  62. #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  63. void board_debug_uart_init(void)
  64. {
  65. at91_seriald_hw_init();
  66. }
  67. #endif
  68. #ifdef CONFIG_BOARD_LATE_INIT
  69. int board_late_init(void)
  70. {
  71. at91_pda_detect();
  72. return 0;
  73. }
  74. #endif
  75. #ifdef CONFIG_BOARD_EARLY_INIT_F
  76. int board_early_init_f(void)
  77. {
  78. #ifdef CONFIG_DEBUG_UART
  79. debug_uart_init();
  80. #endif
  81. return 0;
  82. }
  83. #endif
  84. int board_init(void)
  85. {
  86. /* adress of boot parameters */
  87. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  88. #ifdef CONFIG_NAND_ATMEL
  89. sama5d3_xplained_nand_hw_init();
  90. #endif
  91. #ifdef CONFIG_CMD_USB
  92. sama5d3_xplained_usb_hw_init();
  93. #endif
  94. #ifdef CONFIG_GENERIC_ATMEL_MCI
  95. sama5d3_xplained_mci0_hw_init();
  96. #endif
  97. return 0;
  98. }
  99. int dram_init(void)
  100. {
  101. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  102. CONFIG_SYS_SDRAM_SIZE);
  103. return 0;
  104. }
  105. /* SPL */
  106. #ifdef CONFIG_SPL_BUILD
  107. void spl_board_init(void)
  108. {
  109. #ifdef CONFIG_SD_BOOT
  110. #ifdef CONFIG_GENERIC_ATMEL_MCI
  111. sama5d3_xplained_mci0_hw_init();
  112. #endif
  113. #elif CONFIG_NAND_BOOT
  114. sama5d3_xplained_nand_hw_init();
  115. #endif
  116. }
  117. static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
  118. {
  119. ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
  120. ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
  121. ATMEL_MPDDRC_CR_NR_ROW_14 |
  122. ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
  123. ATMEL_MPDDRC_CR_ENRDM_ON |
  124. ATMEL_MPDDRC_CR_NB_8BANKS |
  125. ATMEL_MPDDRC_CR_NDQS_DISABLED |
  126. ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
  127. ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
  128. /*
  129. * As the DDR2-SDRAm device requires a refresh time is 7.8125us
  130. * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks
  131. */
  132. ddr2->rtr = 0x411;
  133. ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
  134. 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
  135. 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
  136. 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
  137. 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
  138. 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
  139. 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
  140. 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
  141. ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
  142. 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
  143. 28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
  144. 26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
  145. ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
  146. 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
  147. 2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
  148. 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
  149. 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
  150. }
  151. void mem_init(void)
  152. {
  153. struct atmel_mpddrc_config ddr2;
  154. ddr2_conf(&ddr2);
  155. /* Enable MPDDR clock */
  156. at91_periph_clk_enable(ATMEL_ID_MPDDRC);
  157. at91_system_clk_enable(AT91_PMC_DDR);
  158. /* DDRAM2 Controller initialize */
  159. ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
  160. }
  161. void at91_pmc_init(void)
  162. {
  163. u32 tmp;
  164. tmp = AT91_PMC_PLLAR_29 |
  165. AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
  166. AT91_PMC_PLLXR_MUL(43) |
  167. AT91_PMC_PLLXR_DIV(1);
  168. at91_plla_init(tmp);
  169. at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3));
  170. tmp = AT91_PMC_MCKR_MDIV_4 |
  171. AT91_PMC_MCKR_CSS_PLLA;
  172. at91_mck_init(tmp);
  173. }
  174. #endif