at91sam9x5ek.c 5.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Atmel Corporation
  4. */
  5. #include <common.h>
  6. #include <init.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/at91sam9x5_matrix.h>
  9. #include <asm/arch/at91sam9_smc.h>
  10. #include <asm/arch/at91_common.h>
  11. #include <asm/arch/at91_rstc.h>
  12. #include <asm/arch/clk.h>
  13. #include <asm/arch/gpio.h>
  14. #include <debug_uart.h>
  15. #include <asm/mach-types.h>
  16. DECLARE_GLOBAL_DATA_PTR;
  17. /* ------------------------------------------------------------------------- */
  18. /*
  19. * Miscelaneous platform dependent initialisations
  20. */
  21. void at91_prepare_cpu_var(void);
  22. #ifdef CONFIG_CMD_NAND
  23. static void at91sam9x5ek_nand_hw_init(void)
  24. {
  25. struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  26. struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  27. unsigned long csa;
  28. /* Enable CS3 */
  29. csa = readl(&matrix->ebicsa);
  30. csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
  31. /* NAND flash on D16 */
  32. csa |= AT91_MATRIX_NFD0_ON_D16;
  33. /* Configure IO drive */
  34. csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
  35. writel(csa, &matrix->ebicsa);
  36. /* Configure SMC CS3 for NAND/SmartMedia */
  37. writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  38. AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  39. &smc->cs[3].setup);
  40. writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
  41. AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
  42. &smc->cs[3].pulse);
  43. writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
  44. &smc->cs[3].cycle);
  45. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  46. AT91_SMC_MODE_EXNW_DISABLE |
  47. #ifdef CONFIG_SYS_NAND_DBW_16
  48. AT91_SMC_MODE_DBW_16 |
  49. #else /* CONFIG_SYS_NAND_DBW_8 */
  50. AT91_SMC_MODE_DBW_8 |
  51. #endif
  52. AT91_SMC_MODE_TDF_CYCLE(1),
  53. &smc->cs[3].mode);
  54. at91_periph_clk_enable(ATMEL_ID_PIOCD);
  55. /* Configure RDY/BSY */
  56. at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  57. /* Enable NandFlash */
  58. at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  59. at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
  60. at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
  61. at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */
  62. at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */
  63. at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
  64. at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
  65. at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
  66. at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1);
  67. at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1);
  68. at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1);
  69. at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1);
  70. at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);
  71. }
  72. #endif
  73. #ifdef CONFIG_BOARD_LATE_INIT
  74. int board_late_init(void)
  75. {
  76. #ifdef CONFIG_DM_VIDEO
  77. at91_video_show_board_info();
  78. #endif
  79. at91_prepare_cpu_var();
  80. return 0;
  81. }
  82. #endif
  83. #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  84. void board_debug_uart_init(void)
  85. {
  86. at91_seriald_hw_init();
  87. }
  88. #endif
  89. #ifdef CONFIG_BOARD_EARLY_INIT_F
  90. int board_early_init_f(void)
  91. {
  92. #ifdef CONFIG_DEBUG_UART
  93. debug_uart_init();
  94. #endif
  95. return 0;
  96. }
  97. #endif
  98. int board_init(void)
  99. {
  100. /* arch number of AT91SAM9X5EK-Board */
  101. gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK;
  102. /* adress of boot parameters */
  103. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  104. #ifdef CONFIG_CMD_NAND
  105. at91sam9x5ek_nand_hw_init();
  106. #endif
  107. #if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI_HCD)
  108. at91_uhp_hw_init();
  109. #endif
  110. return 0;
  111. }
  112. int dram_init(void)
  113. {
  114. gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
  115. CONFIG_SYS_SDRAM_SIZE);
  116. return 0;
  117. }
  118. #if defined(CONFIG_SPL_BUILD)
  119. #include <spl.h>
  120. #include <nand.h>
  121. void at91_spl_board_init(void)
  122. {
  123. #ifdef CONFIG_SD_BOOT
  124. at91_mci_hw_init();
  125. #elif CONFIG_NAND_BOOT
  126. at91sam9x5ek_nand_hw_init();
  127. #endif
  128. }
  129. #include <asm/arch/atmel_mpddrc.h>
  130. static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
  131. {
  132. ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
  133. ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
  134. ATMEL_MPDDRC_CR_NR_ROW_13 |
  135. ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
  136. ATMEL_MPDDRC_CR_NB_8BANKS |
  137. ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
  138. ddr2->rtr = 0x411;
  139. ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
  140. 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
  141. 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
  142. 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
  143. 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
  144. 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
  145. 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
  146. 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
  147. ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
  148. 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
  149. 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
  150. 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
  151. ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
  152. 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
  153. 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
  154. 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
  155. 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
  156. }
  157. void mem_init(void)
  158. {
  159. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  160. struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  161. struct atmel_mpddrc_config ddr2;
  162. unsigned long csa;
  163. ddr2_conf(&ddr2);
  164. /* enable DDR2 clock */
  165. writel(AT91_PMC_DDR, &pmc->scer);
  166. /* Chip select 1 is for DDR2/SDRAM */
  167. csa = readl(&matrix->ebicsa);
  168. csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
  169. csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
  170. csa |= AT91_MATRIX_EBI_DBPD_OFF;
  171. csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
  172. writel(csa, &matrix->ebicsa);
  173. /* DDRAM2 Controller initialize */
  174. ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
  175. }
  176. #endif