aristainetos-v2.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2015
  4. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  5. *
  6. * Based on:
  7. * Copyright (C) 2012 Freescale Semiconductor, Inc.
  8. *
  9. * Author: Fabio Estevam <fabio.estevam@freescale.com>
  10. */
  11. #include <init.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch/imx-regs.h>
  14. #include <asm/arch/iomux.h>
  15. #include <asm/arch/mx6-pins.h>
  16. #include <env.h>
  17. #include <linux/errno.h>
  18. #include <asm/gpio.h>
  19. #include <asm/mach-imx/iomux-v3.h>
  20. #include <asm/mach-imx/boot_mode.h>
  21. #include <asm/mach-imx/mxc_i2c.h>
  22. #include <asm/mach-imx/video.h>
  23. #include <mmc.h>
  24. #include <fsl_esdhc_imx.h>
  25. #include <miiphy.h>
  26. #include <netdev.h>
  27. #include <asm/arch/mxc_hdmi.h>
  28. #include <asm/arch/crm_regs.h>
  29. #include <linux/fb.h>
  30. #include <ipu_pixfmt.h>
  31. #include <asm/io.h>
  32. #include <asm/arch/sys_proto.h>
  33. #include <pwm.h>
  34. #include <micrel.h>
  35. #include <spi.h>
  36. #include <video.h>
  37. #include <../drivers/video/imx/ipu.h>
  38. #if defined(CONFIG_VIDEO_BMP_LOGO)
  39. #include <bmp_logo.h>
  40. #endif
  41. #define USDHC2_PAD_CTRL (PAD_CTL_SPEED_LOW | \
  42. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  43. #if (CONFIG_SYS_BOARD_VERSION == 2)
  44. /* 4.3 display controller */
  45. #define ECSPI1_CS0 IMX_GPIO_NR(4, 9)
  46. #define ECSPI4_CS0 IMX_GPIO_NR(3, 29)
  47. #elif (CONFIG_SYS_BOARD_VERSION == 3)
  48. #define ECSPI1_CS0 IMX_GPIO_NR(2, 30) /* NOR flash */
  49. /* 4.3 display controller */
  50. #define ECSPI1_CS1 IMX_GPIO_NR(4, 10)
  51. #endif
  52. #define SOFT_RESET_GPIO IMX_GPIO_NR(7, 13)
  53. #define SD2_DRIVER_ENABLE IMX_GPIO_NR(7, 8)
  54. struct i2c_pads_info i2c_pad_info3 = {
  55. .scl = {
  56. .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
  57. .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
  58. .gp = IMX_GPIO_NR(1, 5)
  59. },
  60. .sda = {
  61. .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
  62. .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
  63. .gp = IMX_GPIO_NR(1, 6)
  64. }
  65. };
  66. struct i2c_pads_info i2c_pad_info4 = {
  67. .scl = {
  68. .i2c_mode = MX6_PAD_GPIO_7__I2C4_SCL | PC,
  69. .gpio_mode = MX6_PAD_GPIO_7__GPIO1_IO07 | PC,
  70. .gp = IMX_GPIO_NR(1, 7)
  71. },
  72. .sda = {
  73. .i2c_mode = MX6_PAD_GPIO_8__I2C4_SDA | PC,
  74. .gpio_mode = MX6_PAD_GPIO_8__GPIO1_IO08 | PC,
  75. .gp = IMX_GPIO_NR(1, 8)
  76. }
  77. };
  78. iomux_v3_cfg_t const uart1_pads[] = {
  79. MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  80. MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  81. MX6_PAD_EIM_D19__UART1_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  82. MX6_PAD_EIM_D20__UART1_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  83. };
  84. iomux_v3_cfg_t const uart2_pads[] = {
  85. MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  86. MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  87. };
  88. iomux_v3_cfg_t const uart3_pads[] = {
  89. MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  90. MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  91. MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  92. MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  93. };
  94. iomux_v3_cfg_t const uart4_pads[] = {
  95. MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  96. MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  97. };
  98. iomux_v3_cfg_t const gpio_pads[] = {
  99. /* LED enable*/
  100. MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
  101. /* LED yellow */
  102. MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),
  103. /* LED red */
  104. #if (CONFIG_SYS_BOARD_VERSION == 2)
  105. MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
  106. #elif (CONFIG_SYS_BOARD_VERSION == 3)
  107. MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
  108. #endif
  109. /* LED green */
  110. MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
  111. /* LED blue */
  112. MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  113. /* spi flash WP protect */
  114. MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
  115. /* spi CS 0 */
  116. MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  117. /* spi bus #2 SS driver enable */
  118. MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
  119. /* RST_LOC# PHY reset input (has pull-down!)*/
  120. MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
  121. /* SD 2 level shifter output enable */
  122. MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
  123. /* SD1 card detect input */
  124. MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
  125. /* SD1 write protect input */
  126. MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
  127. /* SD2 card detect input */
  128. MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
  129. /* SD2 write protect input */
  130. MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  131. /* Touchscreen IRQ */
  132. MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
  133. };
  134. static iomux_v3_cfg_t const misc_pads[] = {
  135. /* USB_OTG_ID = GPIO1_24*/
  136. MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
  137. /* H1 Power enable = GPIO1_0*/
  138. MX6_PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
  139. /* OTG Power enable = GPIO4_15*/
  140. MX6_PAD_KEY_ROW4__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
  141. };
  142. iomux_v3_cfg_t const enet_pads[] = {
  143. MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  144. MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  145. MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  146. MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  147. MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  148. MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  149. MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  150. MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  151. MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  152. MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  153. MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  154. MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  155. MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  156. MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  157. MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  158. };
  159. static iomux_v3_cfg_t const backlight_pads[] = {
  160. /* backlight PWM brightness control */
  161. MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
  162. /* backlight enable */
  163. MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
  164. /* LCD power enable */
  165. MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
  166. };
  167. static iomux_v3_cfg_t const ecspi1_pads[] = {
  168. MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  169. MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  170. MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  171. #if (CONFIG_SYS_BOARD_VERSION == 2)
  172. MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(SPI_PAD_CTRL),
  173. #elif (CONFIG_SYS_BOARD_VERSION == 3)
  174. MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(SPI_PAD_CTRL),
  175. MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  176. #endif
  177. };
  178. static void setup_iomux_enet(void)
  179. {
  180. imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  181. }
  182. #if (CONFIG_SYS_BOARD_VERSION == 2)
  183. iomux_v3_cfg_t const ecspi4_pads[] = {
  184. MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL),
  185. MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL),
  186. MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL),
  187. MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
  188. MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  189. };
  190. #endif
  191. static iomux_v3_cfg_t const display_pads[] = {
  192. MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL),
  193. MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
  194. MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
  195. MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
  196. MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
  197. MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
  198. MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
  199. MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
  200. MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
  201. MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
  202. MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
  203. MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
  204. MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
  205. MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
  206. MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
  207. MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
  208. MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
  209. MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
  210. MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
  211. MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
  212. MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
  213. MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
  214. MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
  215. MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
  216. MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
  217. MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
  218. MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
  219. MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
  220. };
  221. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  222. {
  223. if (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
  224. #if (CONFIG_SYS_BOARD_VERSION == 2)
  225. return IMX_GPIO_NR(5, 2);
  226. if (bus == 0 && cs == 0)
  227. return IMX_GPIO_NR(4, 9);
  228. #elif (CONFIG_SYS_BOARD_VERSION == 3)
  229. return ECSPI1_CS0;
  230. if (bus == 0 && cs == 1)
  231. return ECSPI1_CS1;
  232. #endif
  233. return -1;
  234. }
  235. static void setup_spi(void)
  236. {
  237. int i;
  238. imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
  239. #if (CONFIG_SYS_BOARD_VERSION == 2)
  240. imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
  241. #endif
  242. for (i = 0; i < 4; i++)
  243. enable_spi_clk(true, i);
  244. gpio_direction_output(ECSPI1_CS0, 1);
  245. #if (CONFIG_SYS_BOARD_VERSION == 2)
  246. gpio_direction_output(ECSPI4_CS1, 0);
  247. /* set cs0 to high (second device on spi bus #4) */
  248. gpio_direction_output(ECSPI4_CS0, 1);
  249. #elif (CONFIG_SYS_BOARD_VERSION == 3)
  250. gpio_direction_output(ECSPI1_CS1, 1);
  251. #endif
  252. }
  253. static void setup_iomux_uart(void)
  254. {
  255. switch (CONFIG_MXC_UART_BASE) {
  256. case UART1_BASE:
  257. imx_iomux_v3_setup_multiple_pads(uart1_pads,
  258. ARRAY_SIZE(uart1_pads));
  259. break;
  260. case UART2_BASE:
  261. imx_iomux_v3_setup_multiple_pads(uart2_pads,
  262. ARRAY_SIZE(uart2_pads));
  263. break;
  264. case UART3_BASE:
  265. imx_iomux_v3_setup_multiple_pads(uart3_pads,
  266. ARRAY_SIZE(uart3_pads));
  267. break;
  268. case UART4_BASE:
  269. imx_iomux_v3_setup_multiple_pads(uart4_pads,
  270. ARRAY_SIZE(uart4_pads));
  271. break;
  272. }
  273. }
  274. int board_phy_config(struct phy_device *phydev)
  275. {
  276. /* control data pad skew - devaddr = 0x02, register = 0x04 */
  277. ksz9031_phy_extended_write(phydev, 0x02,
  278. MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
  279. MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  280. /* rx data pad skew - devaddr = 0x02, register = 0x05 */
  281. ksz9031_phy_extended_write(phydev, 0x02,
  282. MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
  283. MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  284. /* tx data pad skew - devaddr = 0x02, register = 0x06 */
  285. ksz9031_phy_extended_write(phydev, 0x02,
  286. MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
  287. MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  288. /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
  289. ksz9031_phy_extended_write(phydev, 0x02,
  290. MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
  291. MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
  292. if (phydev->drv->config)
  293. phydev->drv->config(phydev);
  294. return 0;
  295. }
  296. int board_eth_init(bd_t *bis)
  297. {
  298. setup_iomux_enet();
  299. return cpu_eth_init(bis);
  300. }
  301. static int rotate_logo_one(unsigned char *out, unsigned char *in)
  302. {
  303. int i, j;
  304. for (i = 0; i < BMP_LOGO_WIDTH; i++)
  305. for (j = 0; j < BMP_LOGO_HEIGHT; j++)
  306. out[j * BMP_LOGO_WIDTH + BMP_LOGO_HEIGHT - 1 - i] =
  307. in[i * BMP_LOGO_WIDTH + j];
  308. return 0;
  309. }
  310. /*
  311. * Rotate the BMP_LOGO (only)
  312. * Will only work, if the logo is square, as
  313. * BMP_LOGO_HEIGHT and BMP_LOGO_WIDTH are defines, not variables
  314. */
  315. void rotate_logo(int rotations)
  316. {
  317. unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT];
  318. unsigned char *in_logo;
  319. int i, j;
  320. if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT)
  321. return;
  322. in_logo = bmp_logo_bitmap;
  323. /* one 90 degree rotation */
  324. if (rotations == 1 || rotations == 2 || rotations == 3)
  325. rotate_logo_one(out_logo, in_logo);
  326. /* second 90 degree rotation */
  327. if (rotations == 2 || rotations == 3)
  328. rotate_logo_one(in_logo, out_logo);
  329. /* third 90 degree rotation */
  330. if (rotations == 3)
  331. rotate_logo_one(out_logo, in_logo);
  332. /* copy result back to original array */
  333. if (rotations == 1 || rotations == 3)
  334. for (i = 0; i < BMP_LOGO_WIDTH; i++)
  335. for (j = 0; j < BMP_LOGO_HEIGHT; j++)
  336. in_logo[i * BMP_LOGO_WIDTH + j] =
  337. out_logo[i * BMP_LOGO_WIDTH + j];
  338. }
  339. static void enable_display_power(void)
  340. {
  341. imx_iomux_v3_setup_multiple_pads(backlight_pads,
  342. ARRAY_SIZE(backlight_pads));
  343. /* backlight enable */
  344. gpio_direction_output(IMX_GPIO_NR(6, 31), 1);
  345. /* LCD power enable */
  346. gpio_direction_output(IMX_GPIO_NR(6, 15), 1);
  347. /* enable backlight PWM 1 */
  348. if (pwm_init(0, 0, 0))
  349. goto error;
  350. /* duty cycle 500ns, period: 3000ns */
  351. if (pwm_config(0, 50000, 300000))
  352. goto error;
  353. if (pwm_enable(0))
  354. goto error;
  355. return;
  356. error:
  357. puts("error init pwm for backlight\n");
  358. return;
  359. }
  360. static void enable_lvds(struct display_info_t const *dev)
  361. {
  362. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  363. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  364. int reg;
  365. s32 timeout = 100000;
  366. /* set PLL5 clock */
  367. reg = readl(&ccm->analog_pll_video);
  368. reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
  369. writel(reg, &ccm->analog_pll_video);
  370. /* set PLL5 to 232720000Hz */
  371. reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
  372. reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x26);
  373. reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
  374. reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
  375. writel(reg, &ccm->analog_pll_video);
  376. writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xC0238),
  377. &ccm->analog_pll_video_num);
  378. writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xF4240),
  379. &ccm->analog_pll_video_denom);
  380. reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
  381. writel(reg, &ccm->analog_pll_video);
  382. while (timeout--)
  383. if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
  384. break;
  385. if (timeout < 0)
  386. printf("Warning: video pll lock timeout!\n");
  387. reg = readl(&ccm->analog_pll_video);
  388. reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
  389. reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
  390. writel(reg, &ccm->analog_pll_video);
  391. /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
  392. reg = readl(&ccm->cs2cdr);
  393. reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
  394. | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  395. reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
  396. | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  397. writel(reg, &ccm->cs2cdr);
  398. reg = readl(&ccm->cscmr2);
  399. reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
  400. writel(reg, &ccm->cscmr2);
  401. reg = readl(&ccm->chsccdr);
  402. reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  403. << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  404. writel(reg, &ccm->chsccdr);
  405. reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
  406. | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
  407. | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
  408. | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
  409. | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
  410. | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
  411. | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
  412. writel(reg, &iomux->gpr[2]);
  413. reg = readl(&iomux->gpr[3]);
  414. reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
  415. | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
  416. << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
  417. writel(reg, &iomux->gpr[3]);
  418. return;
  419. }
  420. static void enable_spi_display(struct display_info_t const *dev)
  421. {
  422. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  423. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  424. int reg;
  425. s32 timeout = 100000;
  426. #if defined(CONFIG_VIDEO_BMP_LOGO)
  427. rotate_logo(3); /* portrait display in landscape mode */
  428. #endif
  429. /*
  430. * set ldb clock to 28341000 Hz calculated through the formula:
  431. * (XRES + LEFT_M + RIGHT_M + HSYNC_LEN) *
  432. * (YRES + UPPER_M + LOWER_M + VSYNC_LEN) * REFRESH)
  433. * see:
  434. * https://community.freescale.com/thread/308170
  435. */
  436. ipu_set_ldb_clock(28341000);
  437. reg = readl(&ccm->cs2cdr);
  438. /* select pll 5 clock */
  439. reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
  440. | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  441. writel(reg, &ccm->cs2cdr);
  442. /* set PLL5 to 197994996Hz */
  443. reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
  444. reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21);
  445. reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
  446. reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
  447. writel(reg, &ccm->analog_pll_video);
  448. writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4),
  449. &ccm->analog_pll_video_num);
  450. writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240),
  451. &ccm->analog_pll_video_denom);
  452. reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
  453. writel(reg, &ccm->analog_pll_video);
  454. while (timeout--)
  455. if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
  456. break;
  457. if (timeout < 0)
  458. printf("Warning: video pll lock timeout!\n");
  459. reg = readl(&ccm->analog_pll_video);
  460. reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
  461. reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
  462. writel(reg, &ccm->analog_pll_video);
  463. /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
  464. reg = readl(&ccm->cs2cdr);
  465. reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
  466. | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  467. reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
  468. | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  469. writel(reg, &ccm->cs2cdr);
  470. reg = readl(&ccm->cscmr2);
  471. reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
  472. writel(reg, &ccm->cscmr2);
  473. reg = readl(&ccm->chsccdr);
  474. reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  475. << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  476. reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
  477. reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET);
  478. reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
  479. reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
  480. writel(reg, &ccm->chsccdr);
  481. reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
  482. | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
  483. | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
  484. | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
  485. | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
  486. | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
  487. | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
  488. writel(reg, &iomux->gpr[2]);
  489. reg = readl(&iomux->gpr[3]);
  490. reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
  491. | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
  492. << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
  493. writel(reg, &iomux->gpr[3]);
  494. imx_iomux_v3_setup_multiple_pads(
  495. display_pads,
  496. ARRAY_SIZE(display_pads));
  497. return;
  498. }
  499. static void setup_display(void)
  500. {
  501. enable_ipu_clock();
  502. enable_display_power();
  503. }
  504. static void setup_iomux_gpio(void)
  505. {
  506. imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
  507. }
  508. static void set_gpr_register(void)
  509. {
  510. struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  511. writel(IOMUXC_GPR1_APP_CLK_REQ_N | IOMUXC_GPR1_PCIE_RDY_L23 |
  512. IOMUXC_GPR1_EXC_MON_SLVE |
  513. (2 << IOMUXC_GPR1_ADDRS0_OFFSET) |
  514. IOMUXC_GPR1_ACT_CS0,
  515. &iomuxc_regs->gpr[1]);
  516. writel(0x0, &iomuxc_regs->gpr[8]);
  517. writel(IOMUXC_GPR12_ARMP_IPG_CLK_EN | IOMUXC_GPR12_ARMP_AHB_CLK_EN |
  518. IOMUXC_GPR12_ARMP_ATB_CLK_EN | IOMUXC_GPR12_ARMP_APB_CLK_EN,
  519. &iomuxc_regs->gpr[12]);
  520. }
  521. int board_early_init_f(void)
  522. {
  523. setup_iomux_uart();
  524. setup_iomux_gpio();
  525. gpio_direction_output(SOFT_RESET_GPIO, 1);
  526. gpio_direction_output(SD2_DRIVER_ENABLE, 1);
  527. setup_display();
  528. set_gpr_register();
  529. return 0;
  530. }
  531. static void setup_i2c4(void)
  532. {
  533. setup_i2c(3, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
  534. &i2c_pad_info4);
  535. }
  536. static void setup_board_gpio(void)
  537. {
  538. /* enable all LEDs */
  539. gpio_request(IMX_GPIO_NR(2, 13), "LED ena"); /* 25 */
  540. gpio_direction_output(IMX_GPIO_NR(1, 25), 0);
  541. /* switch off Status LEDs */
  542. #if (CONFIG_SYS_BOARD_VERSION == 2)
  543. gpio_request(IMX_GPIO_NR(6, 16), "LED yellow"); /* 176 */
  544. gpio_direction_output(IMX_GPIO_NR(6, 16), 1);
  545. gpio_request(IMX_GPIO_NR(2, 28), "LED red"); /* 60 */
  546. gpio_direction_output(IMX_GPIO_NR(2, 28), 1);
  547. gpio_request(IMX_GPIO_NR(5, 4), "LED green"); /* 132 */
  548. gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
  549. gpio_request(IMX_GPIO_NR(2, 29), "LED blue"); /* 61 */
  550. gpio_direction_output(IMX_GPIO_NR(2, 29), 1);
  551. #elif (CONFIG_SYS_BOARD_VERSION == 3)
  552. gpio_request(IMX_GPIO_NR(6, 16), "LED yellow"); /* 176 */
  553. gpio_direction_output(IMX_GPIO_NR(6, 16), 0);
  554. gpio_request(IMX_GPIO_NR(5, 0), "LED red"); /* 128 */
  555. gpio_direction_output(IMX_GPIO_NR(5, 0), 0);
  556. gpio_request(IMX_GPIO_NR(5, 4), "LED green"); /* 132 */
  557. gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
  558. gpio_request(IMX_GPIO_NR(2, 29), "LED blue"); /* 61 */
  559. gpio_direction_output(IMX_GPIO_NR(2, 29), 0);
  560. #endif
  561. }
  562. static void setup_board_spi(void)
  563. {
  564. /* enable spi bus #2 SS drivers (and spi bus #4 SS1 for rev2b) */
  565. gpio_direction_output(IMX_GPIO_NR(6, 6), 1);
  566. }
  567. int board_late_init(void)
  568. {
  569. char *my_bootdelay;
  570. char bootmode = 0;
  571. char const *panel = env_get("panel");
  572. /*
  573. * Check the boot-source. If booting from NOR Flash,
  574. * disable bootdelay
  575. */
  576. gpio_request(IMX_GPIO_NR(7, 6), "bootsel0");
  577. gpio_direction_input(IMX_GPIO_NR(7, 6));
  578. gpio_request(IMX_GPIO_NR(7, 7), "bootsel1");
  579. gpio_direction_input(IMX_GPIO_NR(7, 7));
  580. gpio_request(IMX_GPIO_NR(7, 1), "bootsel2");
  581. gpio_direction_input(IMX_GPIO_NR(7, 1));
  582. bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 6)) ? 1 : 0) << 0;
  583. bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 7)) ? 1 : 0) << 1;
  584. bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 1)) ? 1 : 0) << 2;
  585. if (bootmode == 7) {
  586. my_bootdelay = env_get("nor_bootdelay");
  587. if (my_bootdelay != NULL)
  588. env_set("bootdelay", my_bootdelay);
  589. else
  590. env_set("bootdelay", "-2");
  591. }
  592. /* if we have the lg panel, we can initialze it now */
  593. if (panel)
  594. if (!strcmp(panel, displays[1].mode.name))
  595. lg4573_spi_startup(CONFIG_LG4573_BUS,
  596. CONFIG_LG4573_CS,
  597. 10000000, SPI_MODE_0);
  598. return 0;
  599. }