board.c 4.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * Board functions for B&R BRXRE1 Board
  6. *
  7. * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
  8. * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
  9. *
  10. */
  11. #include <common.h>
  12. #include <env.h>
  13. #include <errno.h>
  14. #include <init.h>
  15. #include <spl.h>
  16. #include <asm/arch/cpu.h>
  17. #include <asm/arch/hardware.h>
  18. #include <asm/arch/omap.h>
  19. #include <asm/arch/ddr_defs.h>
  20. #include <asm/arch/clock.h>
  21. #include <asm/arch/gpio.h>
  22. #include <asm/arch/sys_proto.h>
  23. #include <asm/arch/mem.h>
  24. #include <asm/io.h>
  25. #include <asm/emif.h>
  26. #include <asm/gpio.h>
  27. #include <dm.h>
  28. #include <power/tps65217.h>
  29. #include "../common/bur_common.h"
  30. #include "../common/br_resetc.h"
  31. /* -------------------------------------------------------------------------*/
  32. /* -- defines for used GPIO Hardware -- */
  33. #define ESC_KEY (0 + 19)
  34. #define LCD_PWR (0 + 5)
  35. #define RSTCTRL_FORCE_PWR_NEN 0x04
  36. #define RSTCTRL_CAN_STB 0x40
  37. DECLARE_GLOBAL_DATA_PTR;
  38. #if defined(CONFIG_SPL_BUILD)
  39. static const struct ddr_data ddr3_data = {
  40. .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  41. .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  42. .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  43. .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  44. };
  45. static const struct cmd_control ddr3_cmd_ctrl_data = {
  46. .cmd0csratio = MT41K256M16HA125E_RATIO,
  47. .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  48. .cmd1csratio = MT41K256M16HA125E_RATIO,
  49. .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  50. .cmd2csratio = MT41K256M16HA125E_RATIO,
  51. .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  52. };
  53. static struct emif_regs ddr3_emif_reg_data = {
  54. .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  55. .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  56. .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  57. .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  58. .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  59. .zq_config = MT41K256M16HA125E_ZQ_CFG,
  60. .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  61. };
  62. static const struct ctrl_ioregs ddr3_ioregs = {
  63. .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  64. .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  65. .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  66. .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  67. .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  68. };
  69. #define OSC (V_OSCK / 1000000)
  70. const struct dpll_params dpll_ddr3 = { 400, OSC - 1, 1, -1, -1, -1, -1};
  71. void am33xx_spl_board_init(void)
  72. {
  73. int rc;
  74. struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
  75. struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
  76. /*
  77. * enable additional clocks of modules which are accessed later from
  78. * VxWorks OS
  79. */
  80. u32 *const clk_domains[] = { 0 };
  81. u32 *const clk_modules_xre1specific[] = {
  82. &cmwkup->wkup_adctscctrl,
  83. &cmper->spi1clkctrl,
  84. &cmper->dcan0clkctrl,
  85. &cmper->dcan1clkctrl,
  86. &cmper->epwmss0clkctrl,
  87. &cmper->epwmss1clkctrl,
  88. &cmper->epwmss2clkctrl,
  89. &cmper->lcdclkctrl,
  90. &cmper->lcdcclkstctrl,
  91. 0
  92. };
  93. do_enable_clocks(clk_domains, clk_modules_xre1specific, 1);
  94. /* power-OFF LCD-Display */
  95. if (gpio_request(LCD_PWR, "LCD_PWR") != 0)
  96. printf("cannot request gpio for LCD_PWR!\n");
  97. else if (gpio_direction_output(LCD_PWR, 0) != 0)
  98. printf("cannot set direction output on LCD_PWR!\n");
  99. /* setup I2C */
  100. enable_i2c_pin_mux();
  101. /* power-ON 3V3 via Resetcontroller */
  102. rc = br_resetc_regset(RSTCTRL_CTRLREG,
  103. RSTCTRL_FORCE_PWR_NEN | RSTCTRL_CAN_STB);
  104. if (rc != 0)
  105. printf("ERROR: cannot write to resetc (turn on PWR_nEN)!\n");
  106. pmicsetup(0, 0);
  107. }
  108. const struct dpll_params *get_dpll_ddr_params(void)
  109. {
  110. return &dpll_ddr3;
  111. }
  112. void sdram_init(void)
  113. {
  114. config_ddr(400, &ddr3_ioregs,
  115. &ddr3_data,
  116. &ddr3_cmd_ctrl_data,
  117. &ddr3_emif_reg_data, 0);
  118. }
  119. #endif /* CONFIG_SPL_BUILD */
  120. /*
  121. * Basic board specific setup. Pinmux has been handled already.
  122. */
  123. int board_init(void)
  124. {
  125. /* request common used gpios */
  126. gpio_request(ESC_KEY, "boot-key");
  127. if (power_tps65217_init(0))
  128. printf("WARN: cannot setup PMIC 0x24 @ bus #0, not found!.\n");
  129. return 0;
  130. }
  131. #ifdef CONFIG_BOARD_LATE_INIT
  132. int board_boot_key(void)
  133. {
  134. return gpio_get_value(ESC_KEY);
  135. }
  136. int board_late_init(void)
  137. {
  138. char othbootargs[128];
  139. br_resetc_bmode();
  140. /* setup othbootargs for bootvx-command (vxWorks bootline) */
  141. snprintf(othbootargs, sizeof(othbootargs),
  142. "u=vxWorksFTP pw=vxWorks o=0x%08x;0x%08x;0x%08x;0x%08x",
  143. (u32)gd->fb_base - 0x20,
  144. (u32)env_get_ulong("vx_memtop", 16, gd->fb_base - 0x20),
  145. (u32)env_get_ulong("vx_romfsbase", 16, 0),
  146. (u32)env_get_ulong("vx_romfssize", 16, 0));
  147. env_set("othbootargs", othbootargs);
  148. /*
  149. * reset VBAR registers to its reset location, VxWorks 6.9.3.2 does
  150. * expect that vectors are there, original u-boot moves them to _start
  151. */
  152. __asm__("ldr r0,=0x20000");
  153. __asm__("mcr p15, 0, r0, c12, c0, 0"); /* Set VBAR */
  154. return 0;
  155. }
  156. #endif /* CONFIG_BOARD_LATE_INIT */